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19-4624; Rev 0; 5/09
Crimzon(R) Infrared Microcontrollers
ZLR64400 ROM MCU
with Learning Amplification
Product Specification
19-4624; Rev 0; 5/09
Maxim Integrated Products Inc. 120 San Gabriel Drive, Sunnyvale CA 94086
Maxim Integrated Products 120 San Gabriel Drive Sunnyvale, CA 94086 United States 408-737-7600 www.maxim-ic.com
Copyright (c) 2009 Maxim Integrated Products Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. Maxim retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Maxim for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. Maxim is a registered trademark of Maxim Integrated Products, Inc. All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their respective holders. Z8 is a registered trademark of Zilog, Inc. Crimzon is a registered trademark of Universal Electronics Inc.
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Revision History
Each instance in the Revision History table reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below.
Page Number All on page 130 on page 130 All
Date April 2009 February 2008 January 2008 July 2007 May 2007
Revision Level 08 07 06 05 04
Description Converted to Maxim product Updated the Ordering Information section. Updated the Ordering Information section. Updated the Disclaimer section and implemented style guide.
Updated Features, 60 , Ordering Information, 1, 120, Part Number Description. Removed 130, 131 PRELIMINARY. Removed TM symbol from LXM core. All Updated Input/Output Port and Clock sections on page in Clock. 86
June 2006 November 2005
03 02
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ZLR64400 ROM MCU Product Specification
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Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Input/Output Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Configuration Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 3 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM Program/Constant Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Pointer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 12 13 18 18 18 19 20 21 22 23 24 26 26 27 28 31 31 34 35 35
Register File Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Infrared Learning Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitting Data Using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . 40 40 41 42 42
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Transmitting Data Using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . Receiving Data Using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . Receiving Data Using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Receive Data Register/UART Transmit Data Register . . . . . . . . . . . . . . UART Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Generator Constant Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T8 TRANSMIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T8 DEMODULATION Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T16 TRANSMIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T16 DEMODULATION Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PING-PONG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 8 Capture High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 8 Capture Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 16 Capture High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 16 Capture Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer 16 High Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer 16 Low Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer 8 High Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer 8 Low Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer 8 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T8 and T16 Common Functions Register . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 16 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 8/Timer 16 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43 44 44 45 47 49 50 51 52 53 54 54 55 58 62 63 64 65 66 66 67 67 68 68 69 69 70 70 72 76 77 79 82 83 85
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Crystal 1 Oscillator Pin (XTAL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Crystal 2 Oscillator Pin (XTAL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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Internal Clock Signals (SCLK and TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Resets and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Power-On Reset Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Reset/Stop Mode Recovery Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Voltage Brownout/Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Fast Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Stop Mode Recovery Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Stop Mode Recovery Event Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SMR Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SMR1 Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 SMR2 Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SMR3 Register Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Stop Mode Recovery Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Z8 LXM CPU Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z8 LXM CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 106 109 110 111 118 118 119 119 120 122
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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Table of Contents
ZLR64400 ROM MCU Product Specification
1
Architectural Overview
Maxim's ZLR64400 ROM MCU is a member of the Crimzon(R) family of infrared microcontrollers. It provides a directly-compatible code upgrade path to other Crimzon MCUs, offers a robust learning function, and features up to 64 KB ROM and 1004 bytes of general-purpose RAM. Two timers allow the generation of complex signals while performing other counting operations. A universal asynchronous receiver/transmitter (UART) allows the ZLR64400 MCU to be a Slave/Master database chip. When the UART is not in use, the baud rate generator (BRG) can be used as a third timer. Enhanced Stop Mode Recovery (SMR) features allow the ZLR64400 MCU to awaken from STOP mode on any change of logic, and on any combination of the 12 SMR inputs. The SMR source can also be used as an interrupt source. Many high-end remote control units offer a learning function. A learning function allows a replacement remote unit to learn most infrared signals from the original remote unit and regenerate the signal. However, the amplifying circuits of many learning remotes are expensive and are not tuned well. Maxim's ZLR64400 MCU is the first chip dedicated to solve this problem because it offers a built-in tuned amplification circuit in a wide range of positions and battery voltages. The only external component required is a photodiode. The ZLR64400 MCU greatly reduces system cost, yet improves learning function reliability. With all new features, the ZLR64400 MCU is excellent for infrared remote control and other MCU applications.
Features
Table 1 lists the memory, I/O, and power features of the ZLR64400 ROM Memory microcontroller. Additional features are listed below the table. Table 1. ZLR64400 ROM MCU Features
Device ZLR64400 MCU ROM (KB) 64 RAM* (Bytes) 1004 I/O Lines 24, or 16 Voltage Range 2.0-3.6 V
*General-purpose registers implemented as random-access memory.
The ZLR64400 MCU supports the following 20 interrupt sources with 6 interrupt vectors:
* * *
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Two from T8, T16 time-out and capture Three from UART Tx, UART Rx, UART BRG One from LVD
Architectural Overview
ZLR64400 ROM MCU Product Specification
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*
14 from SMR source P20-P27, P30-P33, P00, P07 - Any change of logic from P20-P27, P30-P33 can generate an interrupt or SMR
Additional features include:
* * *
IR learning amplifier Low power consumption--8 mW (typical) Three standby modes: - STOP--1.8 A (typical) - HALT--0.8 mA (typical) - Low voltage reset Intelligent counter/timer architecture to automate generation or reception and demodulation of complex waveform and pulsed signals: - One programmable 8-bit counter/timer with two capture registers and two load registers - One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair - Programmable input glitch filter for pulse reception - The UART baud rate generator can be used as another 8-bit timer when the UART is not in use Six priority interrupts - Three external/UART interrupts - Two assigned to counter/timers - One low-voltage detection interrupt 8-bit UART - RX, TX interrupts - 4800, 9600, 19200 and 38400 baud rates - Parity Odd/Even/None - Stop bits 1/2 Low voltage detection and high voltage detection Flags Programmable Watchdog Timer (WDT)/Power-On Reset (POR) circuits Two on-board analog comparators with independent reference voltages and programmable interrupt polarity User selectable options through option bit mask coding (ON/OFF) - Port 0 pins 0-3 pull-up transistors - Port 0 pins 4-7 pull-up transistors - Port 2 pins 0-7 pull-up transistors
*
*
*
* * * *
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Features
ZLR64400 ROM MCU Product Specification
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- - Note:
Port 3 pins 0-3 pull-up transistors Watchdog Timer enabled at Power-on reset
All signals with an overline, " ", are active Low. For example, B/W, in which WORD is active Low, and B/W, in which BYTE is active Low. Power connections use the conventional descriptions listed in Table 2. Table 2. Power Connections
Connection Power Ground Circuit VCC GND Device VDD VSS
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Features
ZLR64400 ROM MCU Product Specification
4
Functional Block Diagram
Figure 1 displays the functional blocks of the ZLR64400 microcontroller.
Figure 1. ZLR64400 MCU Functional Block Diagram
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Functional Block Diagram
ZLR64400 Product Specification
5
Pin Description
Figure 2 displays the pin configuration of the ZLR64400 device in the 20-pin PDIP, SOIC, and SSOP packages.
Figure 2. ZLR64400 MCU 20-Pin PDIP/SOIC/SSOP Pin Configuration
20 19 18 17 16 15 14 13 12 11
P25 P26 P27 P07 VDD XTAL2 XTAL1 P31 P32 P33
1 2 3 4 5 6 7 8 9 10
20-Pin PDIP SOIC SSOP
P24 P23 P22 P21 P20 VSS P01 P00/P30 P36 P34
Table 3 lists the functions and signal directions of each pin within the 20-pin PDIP, SOIC, and SSOP packages sequentially by pin.
Table 3. ZLR64400 MCU 20-Pin PDIP/SOIC/SSOP Sequential Pin Identification Pin No 1 2 3 4 5 6 7 8 9 10 11 12 Symbol P25 P26 P27 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 P36 Function Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 0, bit 7 Power Supply Crystal oscillator Crystal oscillator Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 3, bit 6 Output Input Input Input Input Output Output Direction Input/Output Input/Output Input/Output Input/Output
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Table 3. ZLR64400 MCU 20-Pin PDIP/SOIC/SSOP Sequential Pin Identification (Continued) Pin No 13 14 15 16 17 18 19 20
1When
Symbol P00 P30 P01 VSS P20 P21 P22 P23 P24
Function Port 0, bit 0 Port 3, bit 0 Port 0, bit 1 Ground Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4
Direction Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
1
the Port 0 high-nibble pull-up option is enabled and the P30 input is Low, current flows through the pull-up to Ground.
Table 4 lists the functions and signal direction of each pin within the 20-pin PDIP, SOIC, and SSOP packages by function.
Table 4. ZLR64400 MCU 20-Pin PDIP/SOIC/SSOP Functional Pin Identification Pin No 131 14 4 16 17 18 19 20 1 2 3 8 9 Symbol P00 P30 P01 P07 P20 P21 P22 P23 P24 P25 P26 P27 P31 P32 Function Port 0, bit 0 Port 3, bit 0 Port 0, bit 1 Port 0, bit 7 Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4 Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 3, bit 1 Port 3, bit 2 Direction Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input
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ZLR64400 Product Specification
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Table 4. ZLR64400 MCU 20-Pin PDIP/SOIC/SSOP Functional Pin Identification (Continued) Pin No 10 11 12 5 15 7 6 Symbol P33 P34 P36 VDD VSS XTAL1 XTAL2
through the pull-up to Ground.
Function Port 3, bit 3 Port 3, bit 4 Port 3, bit 6 Power Supply Ground Crystal oscillator Crystal oscillator
Direction Input Output Output
Input Output
1When the Port 0 high-nibble pull-up option is enabled and the P30 input is Low, current flows
Figure 3 displays the pin configuration of the ZLR64400 device in the 28-pin PDIP, SOIC, and SSOP packages.
Figure 3.ZLR64400 MCU 28-Pin PDIP/SOIC/SSOP Pin Configuration
P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
28-Pin PDIP SOIC SSOP
P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35
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ZLR64400 Product Specification
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Table 5 lists the functions and signal directions of each pin within the 28-pin PDIP, SOIC, and SSOP packages sequentially by pin.
Table 5. ZLR64400 MCU 28-Pin PDIP/SOIC/SSOP Sequential Pin Identification Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 P35 P37 P36 P30 P00 P01 P02 VSS P03 P20 P21 P22 P23 P24 Function Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 0, bit 4 Port 0, bit 5 Port 0, bit 6 Port 0, bit 7 Power supply Crystal oscillator Crystal oscillator Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 3, bit 5 Port 3, bit 7 Port 3, bit 6 Port 3, bit 0; connect to VCC if not used Port 0, bit 0 Port 0, bit 1 Port 0, bit 2 Ground Port 0, bit 3 Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4 Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Input Input Output Output Output Output Input Input/Output Input/Output Input/Output Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
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ZLR64400 Product Specification
9
Table 6 lists the functions and signal directions of each pin within the 28-pin PDIP, SOIC, and SSOP packages by function.
Table 6. ZLR64400 MCU 28-Pin PDIP/SOIC/SSOP Functional Pin Identification Pin 19 20 21 23 4 5 6 7 24 25 26 27 28 1 2 3 18 11 12 13 14 15 17 16 8 22 10 9 Symbol P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 VDD VSS XTAL1 XTAL2 Function Port 0, bit 0 Port 0, bit 1 Port 0, bit 2 Port 0, bit 3 Port 0, bit 4 Port 0, bit 5 Port 0, bit 6 Port 0, bit 7 Port 2, bit 0 Port 2, bit 1 Port 2, bit 2 Port 2, bit 3 Port 2, bit 4 Port 2, bit 5 Port 2, bit 6 Port 2, bit 7 Port 3, bit 0; connect to VCC if not used Port 3, bit 1 Port 3, bit 2 Port 3, bit 3 Port 3, bit 4 Port 3, bit 5 Port 3, bit 6 Port 3, bit 7 Power supply Ground Crystal oscillator Crystal oscillator Input Output Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Output Output Output Output
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-
ZLR64400 ROM MCU Product Specification
10
Input/Output Port Pin Functions
The ZLR64400 MCU features three 8-bit ports, which are described below:
* * *
Note:
Port 0 is nibble-programmable as either input or output. Port 2 is bit-programmable as either input or output. Port 3 features four inputs on the lower nibble and four outputs on the upper nibble.
Port 0 and 2 internal pull-ups are disabled on any pin or group of pins when programmed into OUTPUT mode.
Caution: The CMOS input buffer for each Port 0 or 2 pin is always connected to the pin, even when the pin is configured as an output. If the pin is configured as an open-drain output and no external signal is applied, a High output state can cause the CMOS input buffer to float. This might lead to excessive leakage current of more than 100 A. To prevent this leakage, connect the pin to an external signal with a defined logic level or ensure its output state is Low, especially during STOP mode. Port 0, 1, and 2 have both input and output capability. The input logic is always present no matter whether the port is configured as input or output. When doing a READ instruction, the MCU reads the actual value at the input logic but not from the output buffer. In addition, the instructions of OR, AND, and XOR have the Read-Modify-Write sequence. The MCU first reads the port, and then modifies the value and load back to the port. Precaution must be taken if the port is configured as open-drain output or if the port is driving any circuit that makes the voltage different from the desired output logic. For example, pins P00-P07 are not connected to anything else. If it is configured as opendrain output with output logic as ONE, it is a floating port and reads back as ZERO. The following instruction sets P00-P07 all Low.
AND P0,#%F0
Table 7 on page 10 summarizes the registers used to control I/O ports. Some port pin functions can also be affected by control registers for other peripheral functions. Table 7. I/O Port Control Registers
Address (Hex) 12-Bit Bank 000 002 003 0-3 0-3 0-3 8-Bit 00 02 03 Register Description Port 0 Port 2 Port 3 Mnemonic Reset P0 P2 P3 XXh XXh 0Xh Page No 20 22 24
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Input/Output Port Pin Functions
ZLR64400 ROM MCU Product Specification
11
Table 7. I/O Port Control Registers (Continued)
Address (Hex) 12-Bit Bank 0F6 0F7 0F8 F00 All All All F 8-Bit F6 F7 F8 00 Register Description Port 2 Mode Register Port 3 Mode Register Port 0 Mode Register Port Configuration Register Mnemonic Reset P2M P3M P01M PCON FFh XXXX_X000b X1 XX_XXX1b XXXX_X1X0b Page No 21 23 19 18
Port 0
Port 0 is an 8-bit, bidirectional, CMOS-compatible port. Its eight I/O lines are configured under software control to create a nibble I/O port. The output drivers are push/pull or open-drain, controlled by bit 2 of the PCON register. If one or both nibbles are required for I/O operation, they must be configured by writing to the Port 0 Mode Register (P01M). After a hardware reset or a Stop Mode Recovery, Port 0 is configured as an input port. Port 0, bit 7 is used as the transmit output of the UART when UART Tx is enabled.The I/O function of Port 0, bit 7 is overridden by the UART serial output (TxD) when UART Tx is enabled (UCTL[7] = 1). The pin must be configured as an output for TxD data to reach the pin (P0M[6] = 0). An optional pull-up transistor is available as an user selectable mask option on all Port 0 bits with nibble select. See the configuration displayed in Figure 4 on page 12.
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Port 0
ZLR64400 ROM MCU Product Specification
12
Figure 4. Port 0 Configuration
Port 2
Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port. Its eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask programmable option bit is available to connect eight pull-up transistors on this port. Bits programmed as outputs are globally programmed as either push/pull or open-drain. The Power-On Reset function resets with the eight bits of Port 2 [P27:20] configured as inputs. Port 2 also has an 8-bit input OR and AND gate and edge detection circuitry, which can be used to wake up the part. P20 can be programmed to access the edge-detection circuitry in DEMODULATION mode. See the configuration displayed in Figure 5 on page 13.
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Port 2
ZLR64400 ROM MCU Product Specification
13
Figure 5. Port 2 Configuration
Port 3
Port 3 is a 8-bit, CMOS-compatible fixed I/O port (see Figure 6 on page 14). Port 3 consists of four fixed inputs (P33:P30) and four fixed outputs (P37:P34). P30, P31, P32, and P33 are standard CMOS inputs with option enabled pull-up transistors and can be configured under software control as interrupts, as receive data input to the UART block, as input to comparator circuits, or as input to the IR learning AMP. P34, P35, P36, and P37 are push/pull outputs, and can be configured as outputs from the counter/timers. The configuration is displayed in Figure 6 on page 14.
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Port 3
ZLR64400 ROM MCU Product Specification
14
Figure 6. Port 3 Configuration P31 can be used as an interrupt, analog comparator input, infrared learning amplifier input, normal digital input pin and as a Stop Mode Recovery source. When bit 2 of the Port 3 Mode Register (P3M) is set, P31 is used as the infrared learning amplifier, IR1. The reference source for IR1 is GND. The infrared learning amplifier is disabled during STOP mode. When bit 1 of P3M is set, the part is in ANALOG mode and the analog comparator, COMP1 is used. The reference voltage for COMP1 is P30 (PREF1). When in ANALOG mode, P30 cannot be read as a digital input when the CPU reads bit 0 of the Port 3
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Port 3
ZLR64400 ROM MCU Product Specification
15
Register; such reads always return a value of 1. Also, when in ANALOG mode, P31 cannot be used as a Stop Mode Recovery source because in STOP mode, the comparator is disabled, and its output will not toggle. The programming of Bit 2 of the P3M register takes precedence over the programming of Bit 1 in determining the function of P31. If both bits are set, P31 functions as an IR learning amplifier instead of an analog comparator. The output of the function selected for P31 can be used as a source for IRQ2 interrupt assertion (see Figure 6 on page 14). The IRQ2 interrupt can be configured to be based upon detecting a rising, falling, or edge-triggered input change using Bits 6 and 7 of the IRQ register. The P31 output stage signal also goes to the Counter/Timer edge detection circuitry in the same way that P20 does. P32 can be used as an interrupt, analog comparator, UART receiver, normal digital input and as a Stop Mode Recovery source. When bit 6 of UCTL is set, P32 functions as a receive input for the UART. When bit 1 of the P3M Register is set, thereby placing the part into ANALOG mode, P32 functions as an analog comparator, Comp2. The reference voltage for Comp2 is P33 (PREF2). P32 can be used as a rising, falling or edge-triggered interrupt, IRQ0, using IRQ register bits 6 and 7. If UART receiver interrupts are not enabled, the UART receive interrupt is used as the source of interrupts for IRQ0 instead of P32. When in ANALOG mode P32 cannot be used as a Stop Mode Recovery source because the comparators are turned OFF in STOP mode. When in ANALOG mode, P33 cannot be read through bit 3 of the Port 3 Register as a digital input by the CPU. In this case, a read of bit 3 of the Port 3 Register indicates whether a Stop Mode Recovery condition exists. Reading a value of 0 indicates that a Stop Mode Recovery condition does exist; if the ZLR64400 MCU is presently in STOP mode, it will exit STOP mode. Reading a value of 1 indicates that no condition exists to remove the ZLR64400 from STOP mode. Additionally, when in ANALOG mode, P33 cannot be used as an interrupt source. Instead, the existence of a Stop Mode Recovery condition can generate an interrupt, if enabled. P33 can be used as a falling-edge interrupt, IRQ1, when not in ANALOG mode. IRQ1 is also used as the UART TX interrupt and the UART BRG interrupt. Only one source is active at a time. If bits 7 and 5 of UCTL are set to 1, IRQ1 will transmit an interrupt when the Transmit Shift Register is empty. If bits 0 and 5 of UCTL are set to 1 and bit 6 of UCTL is cleared to 0, the BRG interrupts will activate IRQ1. Note: Comparators and the IR amplifier are powered down by entering STOP mode. For P30:P33 to be used as a Stop Mode Recovery source during STOP mode, these inputs must be placed into DIGITAL mode. When in ANALOG mode, do not configure any Port 3 input as a Stop Mode Recovery source. The configuration of these inputs must be re-initialized after Stop Mode Recovery or Power-On Reset.
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Port 3
ZLR64400 ROM MCU Product Specification
16
2
Table 8.Summary of Port 3 Pin Functions
Pin P30 P31 P32 P33 P34 P35 P36 P37 I/O IN IN IN IN OUT OUT OUT OUT T8 T16 T8/T16 AO2 IN Counter/Timers Comparator Interrupt IRAMP REF1 AN1 AN2 REF2 AO1 IRQ2 IRQ0 IRQ1 IROUT IR1 UART Rx UART
Port 3 also provides output for each of the counter/timers and the AND/OR Logic (see Figure 7 on page 17). Control is performed by programming CTR1 bits 5 and 4, CTR0 bit 0, and CTR2 bit 0.
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Port 3
ZLR64400 ROM MCU Product Specification
17
CTR0, bit 0
P34 Data T8_Out
PCON, bit 0 MUX VDD
MUX Pad P3M D2 P31 I REF + - P34
IR1
P3M D1 CTR2, bit 0 + -
VDD
P30
Comp1
P35 Data T16_Out
MUX Pad P35
CTR1, bit 6 VDD P36 Data T8/16_Out
MUX Pad P36
PCON, bit 0 VDD P37 Data P3M D1 P32 P32 P33 + - MUX Pad P37
Comp2
Figure 7. Port 3 Counter/Timer Output Configuration
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Port 3
ZLR64400 ROM MCU Product Specification
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Comparator Inputs
In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference is supplied by P33 and PREF1. In this mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the Stop Mode Recovery sources (excluding P31, P32, and P33) as displayed in Figure 6 on page 14. In DIGITAL mode, P33 is used as bit 3 of the Port 3 input register, which then generates IRQ1. Note: Comparators are powered down by entering STOP mode. For P30:P33 to be used as a Stop Mode Recovery source, these inputs must be placed in DIGITAL mode.
Comparator Outputs
The comparators can be programmed to be output on P34 and P37 by setting bit 0 of the PCON Register.
Port Configuration Register (PCON)
The Port Configuration (PCON) register (Table 9) configures the Port 0 output mode and the comparator output on Port 3. The PCON register is located in expanded register Bank F, address 00h. Table 9. Port Configuration Register (PCON)
Bit Field Reset R/W Address Bit Position [7:3] [2] 0 1 [1] [0] 0 1 -- X 7 6 5 4 3 2 Port 0 Output Mode X 1 W 1 Reserved X -- 0 Comp./IR Amp. Output Port 3 0 W
Reserved X X -- X
Bank F: 00h; Linear: F00h
Value Description -- Reserved--Writes have no effect; reads 11111b. Port 0 Output Mode--Controls the output mode of port 0. Write only; reads return 1. Open-drain Push/pull Reserved--Writes have no effect; reads 1. Comparator or IR Amplifier Output Port 3--Select digital outputs or comparator and IR amplifier outputs on P34 and P37. Write only; reads return 1. P34 and P37 outputs are digital. P34 is Comparator 1 or IR Amplifier output, P37 is Comparator 2 output.
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Port 3
ZLR64400 ROM MCU Product Specification
19
Note:
This register is not reset after a Stop Mode Recovery.
Port 0 Mode Register
The Port 0 Mode Register determines the I/O direction of Port 0. The Port 0 direction is nibble-programmable. Bit 6 controls the upper nibble of Port 0, bits [7:3]. Bit 0 controls the lower nibble of Port 0, bits [3:0]. See Table 10. Table 10. Port 0 Mode Register (P01M)
Bit Field Reset R/W Address Bit Position 7 [6] 0 1 [5:1] [0] 0 1 -- 7 Reserved X -- 6 P07:P04 Mode 1 W X -- X -- 5 4 3 Reserved X -- X -- X -- 2 1 0 P03:P00 Mode 1 W
Bank Independent: F8h; Linear: 0F8h
Value Description 0 Reserved--Writes have no effect. Reads 1b. P07:P04 Mode Output. Input. Reserved--Writes have no effect. Reads 11111b. P00:P03 Mode Output. Input.
Note:
Only P00, P01, and P07 are available on Crimzon(R) ZLR64400 MCU 20-pin configurations.
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Port 0 Mode Register
ZLR64400 ROM MCU Product Specification
20
Port 0 Register
The Port 0 Register allows read and write access to the Port 0 pins (Table 11). Table 11. Port 0 Register (P0)
Bit Field Reset R/W Address Bit Position [7] Read: 0 1 Write: 0 1 [6:0] Read: 0 1 Write: 0 1 7 P07 X R/W 6 P06 X R/W 5 P05 X R/W 4 P04 X R/W 3 P03 X R/W 2 P02 X R/W 1 P01 X R/W 0 P00 X R/W
Bank 0-3: 00h; Linear: 000h
R/W
Description Port 0 Pin 7--Available for I/O if UART Tx is disabled. (Pin configured as input or output in P01M register.) Pin level is Low. Pin level is High. (Pin configured as output in P01M register, UCTL[7]=0.) Assert pin Low. Assert pin High if configured as push-pull; make pin high-impedance if it is open drain. Port 0 Pins 6-0--Each bit provides access to the corresponding Port 0 pin. (Pin configured as input or output in P01M register.) Pin level is Low. Pin level is High. (Pin configured as output in P01M register.) Assert pin Low. Assert pin High if configured as push-pull; make pin high-impedance if it is open-drain.
Note:
Only P00, P01, and P07 are available on Crimzon ZLR64400 MCU 20-pin configurations.
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Port 0 Register
ZLR64400 ROM MCU Product Specification
21
Port 2 Mode Register
The Port 2 Mode Register determines the I/O direction of each bit on Port 2. Bit 0 of the Port 3 Mode Register determines whether the output drive is push/pull or open-drain. See Table 12. Table 12. Port 2 Mode Register (P2M)
Bit Field Reset R/W Address Bit Position [7] [6] [5] [4] [3] [2] [1] [0] 7 P27 I/O Definition 1 R/W 6 P26 I/O Definition 1 R/W 5 P25 I/O Definition 1 R/W 4 P24 I/O Definition 1 R/W 3 P23 I/O Definition 1 R/W 2 P22 I/O Definition 1 R/W 1 P21 I/O Definition 1 R/W 0 P20 I/O Definition 1 R/W
Bank Independent: F6h; Linear: 0F6h
Value Description 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Defines P27 as output. Defines P27 as input. Defines P26 as output. Defines P26 as input. Defines P25 as output. Defines P25 as input. Defines P24 as output. Defines P24 as input. Defines P23 as output. Defines P23 as input. Defines P22 as output. Defines P22 as input. Defines P21 as output. Defines P21 as input. Defines P20 as output. Defines P20 as input.
Note:
This register is not reset after a Stop Mode Recovery.
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Port 2 Mode Register
ZLR64400 ROM MCU Product Specification
22
Port 2 Register
The Port 2 Register allows read and write access to the Port 2 pins. See Table 13. Table 13. Port 2 Register (P2)
Bit Field Reset R/W Address Bit Position [7:0] Read: 0 1 Write: 0 1 7 P27 X R/W 6 P26 X R/W 5 P25 X R/W 4 P24 X R/W 3 P23 X R/W 2 P22 X R/W 1 P21 X R/W 0 P20 X R/W
Bank 0-3: 02h; Linear: 002h
Value Description Port 2 Pins 7-0--Each bit provides access to the corresponding Port 2 pin. (Pin configured as input or output in P2M register.) Pin level is Low. Pin level is High. (Pin configured as output in P2M register.) Assert pin Low. Assert pin High if configured as push-pull; make pin high-impedance if it is open-drain.
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Port 2 Register
ZLR64400 ROM MCU Product Specification
23
Port 3 Mode Register
The Port 3 Mode Register is used primarily to configure the functionality of the Port 3 inputs. When bit 2 is set, the IR Learning Amplifier is used instead of the COMP1 comparator, regardless of the value of bit 1. See Table 14. Table 14. Port 3 Mode Register (P3M)
Bit Field Reset R/W Address Bit Position [7:3] [2] [1] X -- X -- 7 6 5 Reserved X -- X -- X -- 4 3 2 IR Learning Amplifier 0 W 1 Digital/Analog Mode 0 W 0 Port 2 OpenDrain 0 W
Bank Independent: F7h; Linear 0F7h
R/W -- W W
Value Description -- 0 1 0 1 Reserved--Writes have no effect. Reads return 11111b. IR Learning Amplifier disabled. IR Learning Amplifier enabled with P31 configured as amplifier input. Digital/Analog Mode P30, P31, P32, P33 are digital inputs. P30, P32, and P33 are comparator inputs. If P3M[2]=0, P31 is also a comparator input. If P3M[2]=1, P31 is the IR amplifier input. Port 2 open-drain. Port 2 push/pull.
[0]
W
0 1
Note:
This register is not reset after a Stop Mode Recovery.
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Port 3 Mode Register
ZLR64400 ROM MCU Product Specification
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Port 3 Register
The Port 3 Register allows read access to port pins P33 through P30 and write access to the port pins P37 through P34. See Table 15. Table 15. Port 3 Register (P3)
Bit Field Reset R/W Address Bit Position [7] 7 P37 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 X R/W 2 P32 X R/W 1 P31 X R/W 0 P30 X R/W
Banks 0-3: 03h; Linear: 003h
Value Description Port 3, pin 7 Output--Writes to this bit do not affect the pin state if write-only register bit PCON[0] has been written with a 1, which configures P37 as the Comparator 1 or Write: IR Amplifier output. P37 asserted Low if PCON[0]=0. 0 P37 asserted High if PCON[0]=0. 1 A read returns the last value written to this bit. Port 3, pin 6 Output--Writes to this bit do not affect the pin state if register bits Write: CTR1[7:6]=01, which configures P36 as the Timer 8 and Timer 16 combined logic output. 0 P36 asserted Low. 1 P36 asserted High. A read returns the last value written to this bit. Port 3, pin 5 Output--Writes to this bit do not affect the pin state if register bit Write: CTR2[0]=1, which configures P35 as the Timer 16 output. P35 asserted Low. 0 P35 asserted High. 1 A read returns the last value written to this bit. Port 3, pin 4 Output--Writes to this bit do not affect the pin state if write only register bit PCON[0]=1, which configures P34 as Comparator 2 output, or register bit CTR0[0]=1, Write: which configures P34 as Timer 8 output. P34 asserted Low. 0 P34 asserted High. 1 A read returns the last value written to this bit.
[6]
[5]
[4]
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Port 3 Register
ZLR64400 ROM MCU Product Specification
25
Bit Position [3]
Value Description Read: Port 3, pin 3 Input--Writing this bit has no effect. If P3M[1]=0: P33 is Low. 0 P33 is High. 1 If P3M[1]=1 or SMR4[4]=1: SMR condition exists. 0 SMR condition does not exist. 1 Read: Port 3, pin 2 Input--Writing this bit has no effect. If P3M[1]=0: P32 input is Low. 0 P32 input is High. 1 If P3M[1]=1: Comparator 2 output is Low. 0 Comparator 2 output is High. 1 Read: Port 3, pin 1 Input--Writing this bit has no effect. If P3M[2:1]=00: P31 input is Low. 0 P31 input is High. 1 If P3M[2:1]=01: Comparator 1 output is Low. 0 Comparator 1 output is High. 1 If P3M[2:1]=10 or 11: IR amplifier output is Low. 0 IR amplifier output is High. 1 Read: Port 3, pin 0 Input--Writing this bit has no effect. If P3M[1]=00: P30 input is Low. 0 P30 input is High. 1 If P3M[1]=1: Reads as 1. 1
[2]
[1]
[0]
Note:
This register is not reset after a Stop Mode Recovery.
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Port 3 Register
ZLR64400 ROM MCU Product Specification
26
Memory and Registers
The Z8 LXM CPU used in the ZLR64400 family of devices incorporate special features to extend the available memory space while maintaining the benefits of a Z8(R) CPU core in consumer and battery operated applications.
ROM Program/Constant Memory
The ZLR64400 family of devices can address up to 64 KB of ROM, used for object code (program instructions and immediate data) and constant data (ROM tables and data constants). The first 12 bytes of the memory are reserved for the six available 16-bit interrupt request (IRQ) vectors. On reset, program execution begins at address 000Ch in the memory. Execution rolls over to the beginning of the memory if the program counter exceeds the address (FFFFh). The entire ROM memory is available for either program code or constant data. Constant data can be accessed only by the Load Constant (LDC and LDCI) instructions. LDC and LDCI use 16-bit addresses to access the memory. Figure 8 on page 27 displays the Program/Constant memory map for the device.
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Memory and Registers
ZLR64400 ROM MCU Product Specification
27
ROM Memory FFFFh
Program or Constants
000Ch (Reset) IRQ 0-5 Vectors 0000h = 16-bit Address
Not to Scale
Figure 8. Program/Constant Memory Map
Register File
This device features 1056 bytes of register file space, organized in 256-byte banks. Bank 0 contains 237 bytes of RAM addressed as general-purpose registers, 4 port addresses (of which one is reserved), and 16 control register addresses. Banks 1, 2, and 3 each contain 256 general-purpose register bytes. Banks D and F each contain 16 addresses for control registers. All other banks are reserved and must not be selected. The current bank is selected for 8-bit direct or indirect addressing by writing Register Pointer bits RP[3:0]. In the current bank, a 16-byte working register group (addressed as R0-R15) is selected by writing RP[7:4]. A working register operand requires only 4 bits of Program Memory. There are 16 working register groups per bank. See Figure 9 on page 29 and Figure 10 on page 30. 8-bit addresses in the range F0h-FFh (and the equivalent 4-bit addresses) are bank-independent, meaning they always access the control registers in Bank 0, regardless of the RP[3:0] value. Addresses in the range 00h-03h always access the Bank 0 Port registers
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Register File
ZLR64400 ROM MCU Product Specification
28
unless Bank D or F is selected. (Port 01h is not implemented in this device.) When Bank D or F is selected, addresses 10h-EFh access the Bank 0 general-purpose registers. The LDX and LDXI instructions or indirect addressing can be used to access the Bank 1-3 registers not accessible by 8-bit or working register addresses (12-bit addresses 100h- 103h, 1F0h-1FFh, 200h-203h, 2F0h-2FFh, 300h-303h, and 3F0h-3FFh). See Linear Memory Addressing on page 31.
Stack
The stack pointer register (SPL) is Bank 0 register FFh. Operations that use the stack pointer always addresses Bank 0, regardless of the RP[3:0] setting. For details about the stack, refer to Z8 LXM CPU Core User Manual (UM0183). This device does not use a stack pointer high byte. Bank 0 register FEh can be used to store user data, see User Data Register on page 35.
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Register File
ZLR64400 ROM MCU Product Specification
29
Banks 1-3
CPU Control F0h-FFh CPU Control F0h-FFh Bank D CPU Control F0h-FFh Bank F CPU Control F0h-FFh
Bank 0 CPU Control F0h-FFh
CPU Control F0h-FFh
General Purpose Registers 04h-EFh
General Purpose Registers 04h-EFh
Bank 0 General Purpose Registers 10h-EFh
Bank 0 General Purpose Registers 10h-EFh
Ports 00h-03h
Ports 00h-03h
Peripheral Control 00h-0Fh
Peripheral Control 00h-0Fh
= Bank-Independent Address (Always Accesses Bank 0) * Compiler's default interrupt service routine working registers. Not to Scale
Figure 9. Register File 8-Bit Banked Address Map
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Register File
ZLR64400 ROM MCU Product Specification
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Active Group
Active Bank
R7 R6 R5 R4
R3 R2 R1 R0
Register Pointer (RP), 0FDh
The upper nibble of the register file address provided by the register pointer specifies the active working register group.
FF Register Group F F0 EF E0 DF D0
4F 40 3F 30 2F 20 1F 10 0F Register Group 1 Register Group 0 I/O Ports (Banks 0-3 Only) 00
* RP = 00: selects Register Bank 0, Working Register Group 0
Specified Working Register Group Register Group 2
The lower nibble of the register file address provided by the instruction points to the specified register
R15 to R0 R15 to R4* R3 to R0*
Figure 10. Register Pointer--Detail
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Register File
ZLR64400 ROM MCU Product Specification
31
Register Pointer Example
R253 R0 = R1 = R2 = R3 = RP = Port Port Port Port 00h 0 1 2 3
But if:
R253 R0 = R1 = R2 = R3 = RP = 0Dh CTR0 CTR1 CTR2 CTR3
The counter/timers are mapped into ERF group D. Access is easily performed using the following code segment.
LD RP, #0Dh LD R0,#xx LD 1, #xx LD R1, 2 LD RP, #7Dh LD 71h, 2 LD R1, 2 ; ; ; ; ; ; ; ; ; Select ERF D for access to Bank D (working register group 0) load CTR0 load CTR1 CTR2 CTR1 Select Expanded Register Bank D and working register group 7 of Bank 0 for access. CTR2 register 71h CTR2 register 71h
Linear Memory Addressing
In addition to using the RP Register to designate a bank and working register group for 8bit or 4-bit addressing, programs can use 12-bit linear addressing to load a register in any other bark to or from a register in the current bank. Linear addressing is implemented in the LDX and LDXI instructions only. Linear addressing treats the register file as if all of the registers are logically ordered end-to-end, as opposed to being grouped into banks and working register groups, as displayed in Figure 11 on page 33. For linear addressing, register file addresses are numbered sequentially from Bank 0, register 00h to Bank 0, register FFh, then continuing with Bank 1, register 00h, and so on up to Bank F, register FFh. Using the LDX and/or the LDXI instructions, either the target or destination register location can be addressed through a 12-bit linear address value stored in a general-purpose register pair. For example, the following code uses linear addressing for the source of a register transfer operation and uses a working register address for the target.
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Register File
ZLR64400 ROM MCU Product Specification
32
SRP #%23 LD R0, #%55 SRP #%12 LD R6, #%03 LD R7, #%20 LD R0, @RR6
;Set working register group 2 in bank 3 ;Load 55 into working register R0 in the current ;group and bank (linear address 320h) ;Set working register group 1 in bank 2 ;Load high byte of source linear address (0320h) ;Load low byte of source linear address (0320h) ;Load linear address 320h contents (55h) into ;working register R0 in the current group and ;bank (linear address 210h)
From the above example, the source register is referenced via a linear address value contained within registers R6 and R7, whereas the destination is referenced via the SRP setting and a working register. For detailed explanation on LDX and LDXI instructions, refer to Z8 LXM CPU Core User Manual (UM0183). Note: The LDE and LDEI instructions that existed in the Z8 CPU are no longer valid; they have been replaced by the LDX and LDXI instructions.
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Register File
ZLR64400 ROM MCU Product Specification
33
Banks 1-3
Bank 0 CPU Control 0F0h-0FFh
Bank D
Bank F
Typical Stack Below 0D0h
General Purpose Registers 004h-0EFh
General Purpose Registers 100h-3FFh
Reserved D10h-DFFh
Reserved F10h-FFFh
Ports 000h-003h
Peripheral Control D00h-D0Fh
Peripheral Control F00h-F0Fh Not to Scale
Figure 11. Register File LDX, LDXI Linear 12-Bit Address Map
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Register File
ZLR64400 ROM MCU Product Specification
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Register Pointer Register
The upper nibble of the register pointer (Table 16) selects which working register group, of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and, in the case of the Crimzon(R) ZLR64400 MCU family, banks 0, 1, 2, 3, F, and D are implemented. A 0h in the lower nibble allows the normal register file (Bank 0) to be addressed. Any other value from 01h to 0Fh exchanges the lower 16 registers to an expanded register bank. Table 16. Register Pointer Register (RP)
Bit Field Reset R/W Address Bit Position [7:4] [3:0] 0 R/W 7 6 5 4 3 2 1 0
Working Register Group Pointer 0 R/W 0 R/W 0 R/W 0 R/W
Register Bank Pointer 0 R/W 0 R/W 0 R/W
Bank Independent: FDh; Linear 0FDh
Value Description Working Register Group Pointer 0h-Fh Determines which 16-byte working group is addressed. Register Bank Pointer 0h-Fh Determines which bank is active.
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Register Pointer Register
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User Data Register
Bank-independent register FEh is available for user data storage. See Table 17. Note: Do not use register FEh as a counter for the DJNZ instruction.
Table 17. User Data Register (USER)
Bit Field Reset R/W Address Bit Position [7:0] X R/W X R/W X R/W X R/W 7 6 5 4 User Data X R/W X R/W X R/W X R/W 3 2 1 0
Bank Independent: FEh; Linear: 0FEh
Value
Description
00h-FFh User Data
Stack Pointer Register
The Stack Pointer register contains the 8-bit address of the stack pointer. The stack pointer resides in Bank 0 of RAM. The stack address is decremented prior to a PUSH operation and incremented after a POP operation. The stack address always points to the data stored at the `top' of the stack (the lowest stack address). During a call instruction, the contents of the Program Counter are saved on the stack. Interrupts cause the contents of the Program Counter and Flags registers to be saved on the stack. An overflow or underflow can occur when the stack address is incremented or decremented during normal operations. You must prevent this occurrence or unpredictable operations will result. See Table 18. Table 18. Stack Pointer Register (SPL)
Bit Field Reset R/W Address Bit Position Description [7:0] Stack Pointer X R/W X R/W X R/W 7 6 5 4 3 2 1 0
Stack Pointer X R/W X R/W X R/W X R/W X R/W
Bank Independent: FFh; Linear: 0FFh
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User Data Register
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Register File Summary
Table 19 maps each linear (12-bit) register file address to the associated register, mnemonic, and reset value. The table also lists the register bank (or banks) and corresponding 8-bit address, if any, for each register, plus a page link to the detailed register diagram. Throughout this book, an `X' in a number denotes an undefined digit. A `--' (dash) in a table cell indicates that the corresponding attribute does not apply to the listed item. Reset value digits highlighted in grey are not reset by a Stop Mode Recovery. Register bit SMR[7] (shown in boldface) is set to 1 instead of reset by a Stop Mode Recovery. Table 19. Register File Address Summary
Address (Hex) 12-Bit 000 001 002 003 004-00F Bank 0-3 0-3 0-3 0-3 0 8-Bit Register Description 00 01 02 03 Port 0 Reserved Port 2 Port 3 Mnemonic Reset P0 -- P2 P3 -- -- --XXh -- XXh 0Xh XXh XXh --Page No 20 -- 22 24 -- -- -- 49 50 51 52 -- 21 23 19
04-0F General-Purpose Registers (Bank 0 Only)
010-0EF 0,D,F 10-EF General-Purpose Registers (Banks 0, D, F) 0F0 0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 All All All All All All All All All F0 F1 F2 F3 F4 F5 F6 F7 F8 Reserved UART Receive/Transmit Data Register UART Status Register UART Control Register UART Baud Rate Generator Constant Reserved Port 2 Mode Register Port 3 Mode Register Port 0 Mode Register
URDATA/ XXh UTDATA UST UCTL BCNST -- P2M P3M P01M 0 0 0 0 _0 0 1 0 b 00h FFh -- FFh XXXX_X0 0 0 b X1 XX_XXX1 b
PS024508-0409
Register File Summary
ZLR64400 ROM MCU Product Specification
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Table 19. Register File Address Summary (Continued)
Address (Hex) 12-Bit 0F9 0FA 0FB 0FC 0FD 0FE 0FF 100-103 104-1EF 1F0-203 204-2EF 2F0-303 304-3EF 3F0-3FF 400-CFF D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 Bank All All All All All All All -- 1 -- 2 -- 3 -- -- D D D D D D D D D D 8-Bit Register Description F9 FA FB FC FD FE FF -- Interrupt Priority Register Interrupt Request Register Interrupt Mask Register Flags Register Register Pointer User Data Register Stack Pointer Register General-Purpose Registers (12-Bit Only) Mnemonic Reset IPR IRQ IMR FLAGS RP USER SPL -- -- -- -- -- -- -- -- CTR0 CTR1 CTR2 CTR3 TC8L TC8H TC16L TC16H LO16 HI16 XXh 00h 0 XXX_XXXXb XXh 00h XXh XXh XXh XXh XXh XXh XXh XXh XXh -- 0 0 0 0 _0 0 0 0 b 0 0 0 0 _0 0 0 0 b 0 0 0 0 _0 0 0 0 b 0 0 0 0 _0 XXXb 00h 00h 00h 00h 00h 00h Page No 83 85 82 109 34 35 35 -- -- -- -- -- -- -- -- 71 73 76 77 70 70 69 69 68 68
04-EF General-Purpose Registers -- General-Purpose Registers (12-Bit Only)
04-EF General-Purpose Registers -- General-Purpose Registers (12-Bit Only)
04-EF General-Purpose Registers -- -- 00 01 02 03 04 05 06 07 08 09 General-Purpose Registers (12-Bit Only) Reserved Counter/Timer 8 Control Register Timer 8 and Timer 16 Common Functions Counter/Timer 16 Control Register Timer 8/Timer 16 Control Register Counter/Timer 8 Low Hold Register Counter/Timer 8 High Hold Register Counter/Timer 16 Low Hold Register Counter/Timer 16 High Hold Register Timer 16 Capture Low Register Timer 16 Capture High Register
PS024508-0409
Register File Summary
ZLR64400 ROM MCU Product Specification
38
Table 19. Register File Address Summary (Continued)
Address (Hex) 12-Bit D0A D0B D0C D0D-D0F D10-DFF F00 F01-F09 F0A F0B F0C F0D F0E F0F F10-FFF Bank D D D D -- F F F F F F F F -- 8-Bit Register Description 0A 0B 0C Timer 8 Capture Low Register Timer 8 Capture High Register Low-Voltage Detection Register Mnemonic Reset LO8 HI8 LVD -- -- PCON -- SMR4 SMR SMR1 SMR2 SMR3 00h 00h 1 1 1 1 _1 0 0 0 b -- -- XXXX_X1 X0 b -- XXX0 _0 0 0 0 b 0 0 1 0 _0 0 0 0 b 00h X0 X0 _0 0 XXb X0h Page No 67 67 91 -- -- 18 -- 104 95 98 100 103 105 --
0D-0F Reserved -- 00 Reserved (8-Bit access goes to Bank 0) Port Configuration Register
01-09 Reserved 0A 0B 0C 0D 0E 0F -- Stop Mode Recovery Register 4 Stop Mode Recovery Register Stop Mode Recovery Register 1 Stop Mode Recovery Register 2 Stop Mode Recovery Register 3 Watchdog Timer Mode Register Reserved (8-Bit access goes to Bank 0)
WDTMR XXXX_1 1 0 1 b -- --
PS024508-0409
Register File Summary
ZLR64400 ROM MCU Product Specification
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Infrared Learning Amplifier
The ZLR64400 MCU's infrared learning amplifier allows you to detect and decode infrared transmissions directly from the output of the receiving diode without the need for external circuitry. See Port 3 on page 13. An IR diode can be connected to the IR amp as displayed in Figure 12. When the IR amp is enabled and an input current is detected on Port 3, pin 1 (P31), the IR amp outputs a logical High value. When the input current is below the switching threshold of the IR amp, the amp outputs a logical Low value. Within the MCU, the IR amp output goes to the capture/timer logic, which can be programmed to demodulate the IR signal. The IR amp output can also be read by the CPU, or drive the Port 3, pin 4 (P34) output if write-only register bit PCON[0] is written with a 1. The IR learning amp can demodulate signals up to a frequency of 500 kHz. A special mode exists that allows you to capture the third, fourth, and fifth edges of the IR amp output and generate an interrupt.
VCC
D1 Photodiode P31 of MCU
Figure 12. Learning Amplification Circuitry with the ZLR64400 MCU For details about programming the timers to demodulate a received signal, see Timers on page 53.
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Infrared Learning Amplifier
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UART
The universal asynchronous receiver/transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The two UARTs use a single 8-bit data mode with selectable parity. The features of UARTs include:
* * * * * * * * *
8-bit asynchronous data transfer Selectable even- and odd-parity generation and checking One or two Stop bits Separate transmit and receive interrupts Framing, overrun, and break detection Separate transmit and receive enables 8-bit baud rate generator (BRG) BRG TIMER mode UART operational during HALT mode
Table 20. UART Control Registers
Address (Hex) 12-Bit 0F1 0F2 0F3 0F4 Bank All All All All 8-Bit F1 F2 F3 F4 Register Description UART Receive/Transmit Data Register UART Status Register UART Control Register UART Baud Rate Generator Constant Mnemonic Reset URDATA/ UTDATA UST UCTL BCNST XXh 0000_0010b 00h FFh Page No 49 50 51 52
Architecture
The UARTs consist of three primary functional blocks: transmitter, receiver, and BRG. The UART transmitter and receiver function independently, but employ the same baud rate and data format. Figure 13 on page 41 displays the UART architecture.
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UART
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RxD
Receive Shifter
Receive Data Register
Control Registers
System Bus
Transmit Data Register
Status Register
Baud Rate Generator
TxD
Transmit Shift Register Transmitter Control
Parity Generator
CTS DE
Figure 13. UART Block Diagram
Operation
The UART channel can be used to communicate with a master microprocessor or as a slave microprocessor, both of which exhibit transmit and receive functionality. The UART channel can be operated either by polling the UART Status register or via interrupts. The UART remains active during HALT mode. If neither the transmitter nor the receiver is enabled, the UART baud rate generator can be used as an additional timer. The UART contains a noise filter for the receiver that can be enabled.
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Data Format
The UART always transmits and receives data in an 8-bit data format, with the least-significant bit occurring first. An even or odd parity bit can be optionally added to the data stream. Each character begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits. Figure 14 and Figure 15 on page 42 display the asynchronous data format employed by the UARTs without parity and with parity, respectively.
Idle state of line Start 0 Data field lsb Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 msb Bit 7 1 2 Stop bit(s)
1
Figure 14. UART Asynchronous Data Format without Parity
1 0
Idle state of line Start
Data field lsb Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 msb Bit 7 Bit 7 1 2 Stop bit(s)
Figure 15. UART Asynchronous Data Format with Parity
Transmitting Data Using the Polled Method
Follow the steps below to transmit data using the polled method of operation: 1. Write to the baud rate generator constant (BCNST) register, address 0F4h, to set the appropriate baud rate. 2. Write a 0 to bit 6 of the P01M register. 3. Write to the UART control register (UCTL) to: (a) Set the transmit enable bit, UCTL[7], to enable the UART for data transmission. (b) If parity is appropriate, set the parity enable bit, UCTL[4] to 1 and select either Even or Odd parity (UCTL[3]).
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4. Check the Transmit Status register bit, UST[2], to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to step 6. If the Transmit Data register is full (indicated by a 0), continue to monitor the UST[2] bit until the Transmit Data register becomes available to receive new data. 5. Write the data byte to the UART Transmit Data register, 0F1h. The transmitter automatically transfers the data to the internal transmit shift register and transmits the data. 6. To transmit additional bytes, return to step 4. 7. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all data in the Transmit Data and internal shift registers has been transmitted. Caution: Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted. Data written while the transmit data status bit is clear (UST[2]=0) overwrites the previous value written, so the previous written value will not be transmitted. Disabling the UART transmitter while the transmit completion status bit is clear (UST[1]=0) can corrupt the byte being transmitted.
Transmitting Data Using the Interrupt-Driven Method
The UART transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission. Follow the steps below to configure the UART for interrupt-driven data transmission: 1. Write to the BCNST register to set the appropriate baud rate. 2. Write a 0 to bit 6 of the P01M register. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the appropriate priority. 5. Write to the UART Control register to: (a) Set the transmit enable bit (UCTL bit 7) to enable the UART for data transmission. (b) Enable parity, if appropriate, and select either even or odd parity. 6. Execute an EI instruction to enable interrupts. 7. Because the transmit buffer is empty, an interrupt is immediately executed. 8. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the internal transmit shift register and transmits the data. 9. Execute the IRET instruction to return from the interrupt-service routine and wait for the Transmit Data register to again become empty.
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10. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all data in the Transmit Data and internal shift registers has been transmitted. Caution: Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted. Data written while the transmit data status bit is clear (UST[2]=0) overwrites the previous value written, so the previous written value will not be transmitted. Disabling the UART transmitter while the transmit completion status bit is clear (UST[1]=0) can corrupt the byte being transmitted.
Receiving Data Using the Polled Method
Follow the steps below to configure the UART for polled data reception: 1. Write to the BCNST register to set the appropriate baud rate. 2. Write to the UART control register (UCTL) to: (a) Set the receive enable bit (UCTL[6]) to enable the UART for data reception. (b) Enable parity, if appropriate and select either even or odd parity. 3. Check the receive status bit in the UART Status register, bit UST[7], to determine if the Receive Data register contains a valid data byte (indicated by a 1). If UST[7] is set to 1 to indicate available data, continue to step 4. If the Receive Data register is empty (indicated by a 0), continue to monitor the UST[7] bit awaiting reception of the valid data. 4. Read data from the UART Receive Data register. 5. Return to step 3 to receive additional data.
Receiving Data Using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow the steps below to configure the UART receiver for interrupt-driven operation: 1. Write to the UART BRG Constant registers to set the appropriate baud rate. 2. Execute a DI instruction to disable interrupts. 3. Write to the interrupt control registers to enable the UART receiver interrupt and set the appropriate priority. 4. Clear the UART Receiver interrupt in the applicable Interrupt Request register. 5. Write to the UART Control register (UCTL) to: (a) Set the receive enable bit (UCTL[6]) to enable the UART for data reception. (b) Enable parity, if appropriate, and select either even or odd parity. 6. Execute an EI instruction to enable interrupts.
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The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Checks the UART Status register to determine the source of the interrupt, whether it is an error, break, or received data. 2. Reads the data from the UART Receive Data register if the interrupt was caused by data available. 3. Clears the UART receiver interrupt in the applicable Interrupt Request register. 4. Executes the IRET instruction to return from the interrupt service routine and await more data.
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition, when the UART primary functionality is disabled, the Baud Rate Generator can also function as a basic timer with interrupt capability. Note: When the UART is set to run at higher baud rates, the UART receiver's service routine might not have enough time to read and manipulate all bits in the UART Status register (especially bits generating error conditions) for a received byte before the next byte is received. You can devise your own hand-shaking protocol to prevent the transmitter from transmitting more data while current data is being serviced. Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Status bit, UST[2], is set to 1. This indicates that the transmitter is ready to accept new data for transmission. The Transmit Status interrupt occurs after the internal transmit shift register has shifted the first bit of data out. At this point, the Transmit Data register can be written with the next character to send. This provides 7 bit periods of latency to load the Transmit Data register before the transmit shift register completes shifting the current character. Writing to the UART Transmit Data register clears the UST[2] bit to 0. The interrupt is cleared by writing a 0 to the Transmit Data register. Receiver Interrupts The receiver generates an interrupt when any of the following occurs:
*
A data byte has been received and is available in the UART Receive Data register. This interrupt can be disabled independent of the other receiver interrupt sources. The received data interrupt occurs once the receive character has been received and placed in the Receive Data register. Software must respond to this received data available condition before the next character is completely received to avoid an overrun error. The interrupt is cleared by reading from the UART Receive Data register.
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*
A break is received. A break is detected when a 0 is sent to the receiver for the full byte plus the parity and stop bits. After a break is detected, it will interrupt immediately if there is no valid data in the Receive Data register. If data is present in the Receive Data register, an interrupt will occur after the UART Receive Data register is read. An overrun is detected. An overrun occurs when a byte of data is received while there is valid data in the UART Receive Data register that has not been read. The interrupt will be generated when you read the UART Receive Data register. The interrupt is cleared by reading the UART Receive Data register. When an overrun error occurs, the additional data byte will not overwrite the data currently stored in the UART Receive Data register. A data framing error is detected. A data framing error is detected when the first stop bit is 0 instead of 1. When configured for 2 stop bits, a data framing error is only detected when the first stop bit is 0. A framing error interrupt is generated when the framing error is detected. Reading the UART Receive Data register clears the interrupt.
*
*
Note:
It is important to ensure that the transmitter uses the same stop bit configuration as the receiver. UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data register. The Break Detect and Overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the UART Status (UST) register is updated to indicate the overrun condition (and Break Detect, if applicable). The UST[7] bit is set to 1 to indicate that the Receive Data register contains a data byte. However, because the overrun error occurred, this byte may not contain valid data and should be ignored. The Break Detect bit, UST[3], indicates if the overrun was caused by a break condition on the line. After reading the status byte indicating an overrun error, the Receive Data register must be read again to clear the error bits is the UART Status 0 register. Updates to the Receive Data register occur only when the next data word is received. UART Data and Error Handling Procedure Figure 16 on page 47 displays the recommended procedure for use in UART receiver interrupt service routines.
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Receiver Ready
Receiver Interrupt
Read Status
No Errors? Yes
Read data that clears the RDA bit and resets the error bits
Read Data
Discard Data
Figure 16. UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the BRG interrupt enable is set, the UART Receiver interrupt asserts when the UART BRG reloads. This action allows the Baud Rate Generator to function as an additional counter if the UART functionality is not employed.
UART Baud Rate Generator
The UART BRG creates a lower frequency baud rate clock for data transmission. The input to the BRG is the system clock. The UART Baud Rate Constant register contains an 8-bit baud rate divisor value (BCNST[7:0]) that sets the data transmission rate (baud rate)
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of the UART. For programmed register values other than 00h, the UART data rate is calculated using the following equation:
System Clock Frequency Hz UART Data Rate bits s = ----------------------------------------------------------------------------------------------------------------------------------------16 UART Baud Rate Divisor Value BCNST
When the UART Baud Rate Low Register is programmed to 00h, the UART data rate is calculated as follows:
System Clock Frequency Hz UART Data Rate bits s = ----------------------------------------------------------------------------------------4096
When the UART BRG is used as a general-purpose counter, the counters time out period can be computed as follows based upon the counters clock input being a divide by 16 of the system clock and the maximum count value being 255:
16 UART Baud Rate Divisor Value BCNST Time Out Period s = ----------------------------------------------------------------------------------------------------------------------------------------System Clock Frequency MHz
Note:
In general, the system clock frequency is the XTAL clock frequency divided by 2. When the UART is disabled, the BRG can function as a basic 8-bit timer with interrupt on time-out. Follow the steps below to configure the BRG as a timer with interrupt on timeout: 1. Disable the UART by clearing the receive and transmit enable bits, UCTL[7:6] to 0. 2. Load the appropriate 8-bit count value into the UART Baud Rate Generator Constant register. The count frequency is the system clock frequency in Hz divided by 16. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the Baud Rate Generator bit (UCTL bit 0) in the UART Control Register to 1. When configured as an 8-bit timer, the count value, instead of the reload value, is read, and the counter begins counting down from its initial programmed value. Upon timing out (reaching a value of 1), if the time-out interrupt is enabled, an interrupt will be produced. The counter will then reload its programmed start value and begin counting down again. Table 21 lists a number of BCNST register settings at various baud rates and system clock frequencies.
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Table 21. BCNST Register Settings Examples
Target UART Data Rate (baud) 2400 4800 9600 19200 System Clock = 4 MHz, Crystal Clock = 8 MHz BCNST = 01101000 Actual baud rate = 2403 BCNST = 00110100 Actual baud rate = 4807 BCNST = 00011010 Actual baud rate = 9615 BCNST = 00001101 Actual baud rate = 19230 System Clock = 3 MHz, Crystal Clock = 6 MHz BCNST = 01001110 Actual baud rate = 2403 BCNST = 00100111 Actual baud rate = 4807 BCNST = 00010100 Actual baud rate = 9375 BCNST = 00001010 Actual baud rate = 18750
UART Receive Data Register/UART Transmit Data Register
The UART Receive/Transmit Data Register is used to send and retrieve data from the UART channel. When the UART receives a byte of data, it can be read from this register. The UART receive interrupt is cleared when this register is used. Data written to this register is transmitted by the UART. See Table 22. Table 22. UART Receive/Transmit Data Register (URDATA/UTDATA)
Bit Field Reset R/W Address X R/W X R/W X R/W 7 6 5 4 X R/W 3 X R/W 2 X R/W 1 X R/W 0 X R/W
UART Receive/Transmit
Bank Independent: F1h; Linear: 0F1h
Bit Position Description [7:0] UART Receive/Transmit When read, returns received data. When written, transmits written data.
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UART Receive Data Register/UART Transmit Data
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UART Status Register
The UART Status Register shows the status of the UART. Bits [6:3] are cleared by reading the UART Receive/Transmit Register (F1h). See Table 23. Table 23. UART Status Register (UST)
Bit Field Reset R/W Address 7 Receive Status 0 R/W 6 Parity Error 0 R/W 5 Overrun Error 0 R/W 4 Framing Error 0 R/W 3 Break 0 R/W 2 Transmit Data 0 R/W 1 Transmit Complete 1 R/W 0 Noise Filter 0 R/W
Bank Independent: F2h; Linear: 0F2h
Bit Position [7]
Value Description 0 1 Receive Status--Set when data is received; cleared when URDATA is read. UART Receive Data Register empty. UART Receive Data Register full. Parity--Set when a parity error occurs; cleared when URDATA is read. No parity error occurs. Parity error occurs. Overrun--Set when an overrun error occurs; cleared when URDATA is read. No overrun error occurs. Overrun error occurs. Framing--Set when a framing error occurs; cleared when URDATA is read. No framing error occurs. Framing error occurs. Break--Set when a break is detected; cleared when URDATA is read. No break occurs. Break occurs. Transmit Data Status--Set when the UART is ready to transmit; cleared when TRDATA is written. Do not write to the UART Transmit Data Register. UART Transmit Data Register ready to receive additional data. Transmit Completion Status Data is currently transmitting. Transmission is complete.
[6] 0 1 [5] 0 1 [4] 0 1 [3] 0 1 [2] 0 1 [1] 0 1
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Bit Position [0]
Value Description Read: Noise Filter--Detects noise during data reception. 0 No noise detected. 1 Noise detected. Write: 0 Turn OFF noise filter. 1 Turn ON noise filter.
UART Control Register
As its name implies, the UART Register controls the UART. In addition to setting bit 5, also set appropriate bit in the Interrupt Mask Register (see Table 44 on page 85). Note: This register is not reset after a Stop Mode Recovery.
Table 24. UART Control Register (UCTL)
Bit Field Reset R/W Address 7 6 5 4 Parity Enable 0 R/W 3 Parity Select 0 R/W 2 Send Break 0 R/W 1 0
Transmitter Receiver UART Interrupts Enable Enable Enable 0 R/W 0 R/W 0 R/W
Stop Bits Baud Rate Generator 0 R/W 0 R/W
Bank Independent: F3h; Linear: 0F3h
Bit Position Value Description [7] [6] [5] [4] [3] 0 1 0 1 0 1 0 1 0 1 Transmitter disabled. Transmitter enabled. Receiver disabled. Receiver enabled. UART Interrupts disabled. UART Interrupts enabled. Parity disabled. Parity enabled. Even parity selected. Odd parity selected.
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UART Control Register
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Bit Position Value Description [2] [1] [0] 0 1 0 1 No break is sent. Send Break (force Tx output to 0). One stop bit. Two stop bits. Baud Rate Generator--When the transmitter and receiver are disabled, the BRG can be used as an additional timer. When setting this bit, clear bits [7:6] in this register. Also set bit [5] if an interrupt is desired when the BRG is reloaded. BRG used as BRG for UART. BRG used as timer.
0 1
Baud Rate Generator Constant Register
The UART BRG determines the frequency at which UART data is received and transmitted. This baud rate is determined by the following formula:
System Clock Frequency Hz UART Data Rate bits s = --------------------------------------------------------------------------------------------------------------------------16 UART Baud Rate Divisor Value BCNST
The system clock is usually the crystal clock divided by 2. When the UART BRG is used as an additional timer, a Read from this register will return the actual value of the count of the BRG in progress and not the reload value. See Table 25. Note: This register is not reset after a Stop Mode Recovery.
Table 25. Baud Rate Generator Constant Register (BCNST)
Bit Field Reset R/W Address 1 R/W 1 R/W 1 R/W 7 6 5 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W
Baud Rate Generator Constant
Bank Independent: F4h; Linear: 0F4h
Bit Position [7:0]
Description BRG Constant When read, returns the actual timer count value (when UCTL[0]=1). When written, sets the Baud Rate Generator Constant. The actual baud rate frequency = XTAL / (32 x BCNST).
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Baud Rate Generator Constant Register
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Timers
The Crimzon(R) ZLR64400 MCU infrared timer contains a 16-bit and an 8-bit counter/ timer, each of which can be used simultaneously for transmitting. In addition, both timers can be used for demodulating an input carrier wave. Both timers share a single input pin. Figure 17 displays the counter/timer architecture, which is designed to help unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveforms and pulses. In addition to the 16-bit and 8-bit timers, the UART's baud rate generator can be used as an additional 8-bit timer when the UART receiver is not in use. See UART on page 40.
HI16
8
LO16
8
16-Bit Timer 16
Timer 16
1
2
4
8
8
16
8
SCLK
Clock Divider
TC16H
TC16L AND/OR Logic Timer 8/16
HI8
LO8
8
8
Glitch Filter
Edge Detect Circuit
8-Bit Timer 8
Timer 8
8
8
TC8H
TC8L
Figure 17. Counter/Timers Block Diagram
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Timers
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Table 26 summarizes the registers used to control timers. Some timer functions can also be affected by control registers for other peripheral functions. Table 26. Timer Control Registers
Address (Hex) 12-Bit D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D0A D0B Bank 8-Bit D D D D D D D D D D D D 00 01 02 03 04 05 06 07 08 09 0A 0B Register Description Counter/Timer 8 Control Register Timer 8 and Timer 16 Common Functions Counter/Timer 16 Control Register Timer 8/Timer 16 Control Register Counter/Timer 8 Low Hold Register Counter/Timer 8 High Hold Register Counter/Timer 16 Low Hold Register Counter/Timer 16 High Hold Register Timer 16 Capture Low Register Timer 16 Capture High Register Timer 8 Capture Low Register Timer 8 Capture High Register Mnemonic Reset CTR0 CTR1 CTR2 CTR3 TC8L TC8H TC16L TC16H LO16 HI16 LO8 HI8 0000_00 0 0 b 0000_00 0 0 b 0000_00 0 0 b 0000_0XXXb 00h 00h 00h 00h 00h 00h 00h 00h Page No 71 73 76 77 70 70 69 69 68 68 67 67
Counter/Timer Functional Blocks
The Crimzon ZLR64400 MCU infrared timer contains a glitch filter for removing noise from the input when demodulating an input carrier. Each timer features its own DEMODULATING mode. The T8 timer has the ability to capture only one cycle of a carrier wave of a high-frequency waveform. Each timer can be simultaneously used to generate a signal output.
Input Circuit
Depending on the setting of register bits P3M[2:1] and CTR1[6], the timer/counter input monitors one of the following conditions:
* * *
The P31 digital signal, if CTR1[6]=0 and P3M[2:1]=00. The P31 analog comparator output, if CTR1[6]=0 and P3M[2:1]=01. The P31 IR amplifier output, if CTR1[6]=0 and P3M[2]=1.
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*
The P20 digital signal, if CTR16=1.
Based on register bits CTR1[5:4], a pulse is generated at when a rising edge, falling edge, or any edge is detected. Glitches in the input signal are filtered out if they are shorter than the glitch filter width specified in register bits CTR1[3:2]. The input circuit is displayed in Figure 18.
P3M[1]
P31 + Comp. - + IR Amp. -
0
P3M[2]
0 1
CTR1[6] CTR1[3:2] Glitch Filter 00 4 SCLK 1 8 SCLK Reserved 01 10 11 00 10 01 11 Reserved CTR1[5:4] Edge Detection 0 Falling Edge Rising Edge CTR1[0] CTR1[1]
P30
1
IREF
P20
Figure 18. Counter/Timer Input Circuit
T8 TRANSMIT Mode
Before T8 is enabled, the output of T8 depends on CTR1, bit 1. If it is 0, T8_OUT is 1; if it is 1, T8_OUT is 0. See Figure 19 on page 56.
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T8 (8-Bit) Transmit Mode
No
T8_Enable Bit Set CTR0, bit 7 Yes
Reset T8_ENABLE Bit 0
CTR1, bit 1 Value
1
Load TC8L Reset T8_OUT
Load TC8H Set T8_OUT
Set Time-Out Status Bit (CTR0 bit 5) and generate TIMEOUT_INT if enabled
Enable T8
No
T8_TIMEOUT Yes
Single Pass
Yes
Single Pass? Modulo-N No 0 T8_OUT Value
1
Load TC8L Reset T8_OUT
Load TC8H Set T8_OUT
Enable T8
Set Time-Out Status Bit (CTR0, bit 5) and generate TIMEOUT_INT if enabled
No T8_TIMEOUT Yes
Figure 19. TRANSMIT Mode Flowchart
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When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, bit 1). If the initial value (CTR1, bit 1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter. In SINGLE-PASS mode (CTR0, Bit 6), T8 counts down to 0 and stops, T8_OUT toggles, the time-out status bit (CTR0, bit 5) is set, and a time-out interrupt can be generated if it is enabled (CTR0, bit 1). In MODULO-N mode, upon reaching terminal count, T8_OUT is toggled, but no interrupt is generated. From that point, T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles T8_OUT, and sets the time-out status bit (CTR0, bit 5), thereby generating an interrupt if enabled (CTR0, bit 1). One cycle is thus completed. T8 then loads from TC8H or TC8L according to the T8_OUT level and repeats the cycle. See Figure 20.
Z8 LXM Data Bus
CTR0 data bit 2
Positive Edge Negative Edge HI8 LO8 IRQ4
CTR0 data bits [4:3] Clock 8-Bit Counter T8 (TC8)
CTR0 data bit 1 Clock Select
SCLK
T8_OUT
TC8H Z8 LXM Data Bus
TC8L
Figure 20. 8-Bit Counter/Timer Circuits You can modify the values in TC8H or TC8L at any time. The new values take effect when they are loaded. Caution: An initial count of 1 is not allowed (a non-function occurs). An initial count of 0 causes TC8 to count from 0 to FFh to FEh. Note: The "h" suffix denotes hexadecimal values. Transition from 0 to FFh is not a time-out condition.
Caution: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended.
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Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must be reset. These commands are required because it takes one counter/timer clock interval for the initiated event to actually occur. See Figure 21 and Figure 22.
TC8H Counts
Counter Enable command; T8_OUT switches to its initial value (CTR1 data bit 1)
T8_OUT toggles; time-out interrupt
Figure 21. T8_OUT in SINGLE-PASS Mode
T8_OUT toggles
T8_OUT
TC8L
TC8H
TC8L
TC8H
TC8L
Counter Enable command, T8_OUT, switches to its initial value (CTR1 data bit 1)
Time-out interrupt
Time-out interrupt
Figure 22. T8_OUT in MODULO-N Mode
T8 DEMODULATION Mode
You must program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1 bits [5:4]) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1 bits [5:4]) is detected during counting, the current value of T8 is complemented and put into one of the capture registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put into HI8. From that point, one of the edge detect status bits (CTR1, bits [1:0]) is set, and an interrupt can be generated if enabled (CTR0, bit 2). Meanwhile, T8 is loaded with FFh and starts counting again. If T8 reaches 0, the time-out status bit (CTR0, bit 5) is set, and an interrupt can be generated if enabled (CTR0, bit 1). T8 then continues counting from FFh. See Figure 23.
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Counter/Timer Functional Blocks
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T8 (8-bit) Count Capture
No
T8_Enable (Set By User)
Yes
Edge Present? No
Yes
Pos
Neg What Kind Of Edge?
T8 LO8
T8 HI8
%FF T8
Figure 23. DEMODULATION Mode Count Capture Flowchart When bit 4 of CTR3 is enabled, the flow of the demodulation sequence is altered. The third edge makes T8 active, and the fourth and fifth edges are captured. The capture interrupt is activated after the fifth event occurs. This mode is useful for capturing the carrier duty cycle as well as the frequency at which the first cycle is corrupted. See Figure 24 and Figure 25 on page 61.
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T8 (8-Bit) Demodulation Mode
No
T8_Enable CTR0, D7? Yes %FF TC8
No
First Edge Present? Yes
Disable T8
Enable TC8
T8_Enable Bit Set? No Yes
No Edge Present?
Yes T8 Time Out? Set Edge Present Status Bit and Trigger Data Capture Int. if Enabled
No
Yes Set Time-Out Status Bit and Trigger Time Out Int. if Enabled
Continue Counting
Figure 24. DEMODULATION Mode Flowchart
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T8 (8-Bit) Demodulation Mode
No
T8_Enable CTR0 bit 7
Yes
FFh TC8
No
Third Edge Present
Yes
Disable T8
Enable TC8
T8_Enable Bit Set No Yes
Fourth Edge Present Yes
No
Fifth Edge Present Yes
Set Edge Present Status Capture interrupt if enabled Set Edge Present Status Bit and Trigger Data No T8 Time Out Yes Set Time-Out Status Bit and Trigger Time Out Interrupt if enabled
Continue Counting
Figure 25. DEMODULATION Mode Flowchart with Bit 4 of CTR3 Set
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T16 TRANSMIT Mode
In NORMAL or PING-PONG mode, the output of T16 when not enabled, is dependent on CTR1, bit 0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force the output of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 bits [3:2] to a 10 or 11. When bit 4 of CTR3 is set, the T16 output does not update. However, time-out interrupts (Flags) are still updated. In addition, the T8 carrier is not disrupted by timing out of the T16 timer. When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its initial value (CTR1, bit 0). When T16 counts down to 0, T16_OUT is toggled (in NORMAL or PING-PONG mode), an interrupt (CTR2, bit 1) is generated (if enabled), and a status bit (CTR2, bit 5) is set. See Figure 26.
Z8 LXM Data Bus
CTR2 data bit 2
Positive Edge Negative Edge HI16 LO16 IRQ3
CTR2 data bits [4:3] Clock Select Clock 16-Bit Counter T16 (TC16)
CTR2 data bit 1
SCLK
T16_OUT
TC16
Z8 LXM Data Bus
TC16
Figure 26. 16-Bit Counter/Timer Circuits Note: Global interrupts override this function as described in the Interrupts on page 79. If T16 is in SINGLE-PASS mode, it is stopped at this point (see Figure 27 on page 63). If it is in MODULO-N mode, it is loaded with TC16H * 256 + TC16L, and the counting continues (see Figure 28 on page 63).
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You can modify the values in TC16H and TC16L at any time. The new values take effect when they are loaded. Caution: Do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. An initial count of 1 is not allowed. An initial count of 0 causes T16 to count from 0 to FFFEh. Transition from 0 to FFFFh is not a time-out condition.
TC16H * 256 + TC16L Counts
Counter Enable command, T16_OUT, switches to its initial value (CTR1 data bit 0)
T16_OUT toggles, Time-out interrupt
Figure 27. T16_OUT in SINGLE-PASS Mode
TC16H * 256 + TC16L
TC16H * 256 + TC16L
T16_OUT
TC16H * 256 + TC16L
Counter Enable command, T16_OUT, switches to its initial value (CTR1 data bit 0)
T16_OUT toggles, Time-out interrupt
T16_OUT toggles, Time-out interrupt
Figure 28. T16_OUT in MODULO-N Mode
T16 DEMODULATION Mode
You must program TC16L and TC16H to FFh. After T16 is enabled, and the first edge (rising, falling, or both depending on CTR1 bits [5:4]) is detected, T16 captures HI16 and LO16, reloads, and begins counting.
If Bit 6 of CTR2 Is 0--When a subsequent edge (rising, falling, or both depending on CTR1 bits [5:4]) is detected during counting, the current count in T16 is complemented and put into HI16 and LO16. When data is captured, one of the edge detect status bits
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(CTR1, bit 1; bit 0) is set, and an interrupt is generated if enabled (CTR2, Bit 2). T16 is loaded with FFFFh and starts again. This T16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks).
If Bit 6 of CTR2 Is 1--T16 ignores the subsequent edges in the input signal and continues counting down. A time-out of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, Bit 2). In this case, T16 does not reload and continues counting. If CTR2 bit 6 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the next edge (rising, falling, or both depending on CTR1 bits [5:4]), continuing to ignore subsequent edges.
This T16 mode generally measures mark time, the length of an active carrier signal burst. If T16 reaches 0, T16 continues counting from FFFFh. Meanwhile, a status bit (CTR2 bit 5) is set, and an interrupt time-out can be generated if enabled (CTR2 bit 1).
PING-PONG Mode
This operation mode is only valid in TRANSMIT mode. T8 and T16 must be programmed in SINGLE-PASS mode (CTR0, bit 6; CTR2, bit 6), and PING-PONG mode must be programmed in CTR1 bits [3:2]. You can begin the operation by enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1, bit 1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT then switches to its initial value (CTR1, bit 0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops, T8 is enabled again, repeating the entire cycle. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0, bit 1; CTR2, bit 1). To stop the Ping-pong operation, write 00 to bits CTR1 bits [3:2]. See Figure 29 on page 65. Note: Enabling Ping-pong operation while the counter/timers are running might cause intermittent counter/timer function. Disable the counter/timers and reset the status flags before instituting this operation.
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Enable TC8
Time-Out
Enable Ping-Pong CTR1 data bits [3:2] TC16
Time-Out
Figure 29. PING-PONG Mode Diagram Initiating PING-PONG Mode First, ensure that both counter/timers are not running. Set T8 into SINGLE-PASS mode (CTR0, bit 6), set T16 into SINGLE-PASS mode (CTR2, bit 6), and set the PING-PONG mode (CTR1 bits [3:2]). These instructions are not consecutive and can occur in random order. Finally, start PING-PONG mode by enabling either T8 (CTR0, D7) or T16 (CTR2, D7). The initial value of T8 or T16 must not be 1. If you stop the timer and restart the timer, reload the initial value to avoid an unknown previous value. During PING-PONG Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by hardware. The time-out bits (CTR0, bit 5; CTR2, bit 5) are set every time the counter/timers reach the terminal count.
Timer Output
The output logic for the timers is displayed in Figure 30 on page 66. P34 is used to output T8_OUT when bit 0 of CTR0 is set. P35 is used to output the value of T16_OUT when bit 0 of CTR2 is set. When bit 6 of CTR1 is set, P36 outputs the logic combination of T8_OUT and T16_OUT via bits [4:5] of CTR1.
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P34_INTERNAL
MUX
P34
CTR0 data bit 0 T8_OUT T16_OUT CTR1 data bit 2 AND/OR/NOR/NAND Logic MUX CTR1 data bit 6 CTR1 data bits [5:4] CTR1 data bit 3 P35_INTERNAL MUX P35 P36_INTERNAL
MUX
P36
CTR2 data bit 0
Figure 30. Output Circuit
Counter/Timer Registers
The following sections describe each of the Timer/Counter registers in detail.
Timer 8 Capture High Register
The Timer 8 Capture High Register holds the captured data from the output of the 8-bit Counter/Timer 0. Typically, this register contains the number of counts when the input signal is 1. Note: This register is not reset after a Stop Mode Recovery.
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Table 27. Timer 8 Capture High Register (HI8)
Bit Field Reset R/W Address Bit Position [7:0] 0 R 0 R 0 R 7 6 5 4 3 2 1 0
T8_Capture_HI 0 R 0 R 0 R 0 R 0 R
Bank D: 0Bh; Linear: D0Bh
Value
Description
0hh-FFh T8_Capture_HI--Reads return captured data. Writes have no effect.
Timer 8 Capture Low Register
The Timer 8 Capture Low Register holds the captured data from the output of the 8-bit Counter/Timer 0. Typically, this register contains the number of counts when the input signal is 0. Note: This register is not reset after a Stop Mode Recovery.
Table 28. Timer 8 Capture Low Register (L08)
Bit Field Reset R/W Address Bit Position [7:0] 0 R 0 R 0 R 7 6 5 4 3 2 1 0
T8_Capture_LO 0 R 0 R 0 R 0 R 0 R
Bank D: 0Ah; Linear: D0Ah
Value
Description
0hh-FFh T8_Capture_LO--Read returns captured data. Writes have no effect.
Timer 16 Capture High Register
The Timer 16 Capture High Register holds the captured data from the output of the 16-bit Counter/Timer 16. This register contains the most significant byte (MSB) of the data. Note: This register is not reset after a Stop Mode Recovery.
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Table 29. Timer 16 Capture High Register (HI16)
Bit Field Reset R/W Address Bit Position [7:0] 0 R 0 R 0 R 7 6 5 4 3 2 1 0
T16_Capture_HI 0 R 0 R 0 R 0 R 0 R
Bank D: 09h; Linear: D09h
Value
Description
0hh-FFh T16_Capture_HI--Read returns captured data. Writes have no effect.
Timer 16 Capture Low Register
The Timer 16 Capture Low Register holds the captured data from the output of the 16-bit Counter/Timer 16. This register contains the LSB of the data. Note: This register is not reset after a Stop Mode Recovery.
Table 30. Timer 16 Capture Low Register (L016)
Bit Field Reset R/W Address Bit Position [7:0] 0 R 0 R 0 R 7 6 5 4 3 2 1 0
T16_Capture_LO 0 R 0 R 0 R 0 R 0 R
Bank D: 08h; Linear: D08h
Value
Description
0hh-FFh T16_Capture_LO--Read returns captured data. Writes have no effect.
Counter/Timer 16 High Hold Register
The Counter/Timer 16 High Hold Register contains the high byte of the value loaded into the T16 timer. Note: This register is not reset after a Stop Mode Recovery.
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Table 31. Counter/Timer 16 High Hold Register (TC16H)
Bit Field Reset R/W Address Bit Position [7:0] 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
T16_Data_HI 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bank D: 07h; Linear: D07h
Value
Description
0hh-FFh T16_Data_HI--Read/Write Data.
Counter/Timer 16 Low Hold Register
The Counter/Timer 16 Low Hold Register contains the low byte of the value loaded into the T16 timer. Note: This register is not reset after a Stop Mode Recovery.
Table 32. Counter/Timer 16 Low Hold Register (TC16L)
Bit Field Reset R/W Address Bit Position [7:0] 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
T16_Data_LO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bank D: 06h; Linear: D06h
Value
Description
0hh-FFh T16_Data_LO--Read/Write Data.
Counter/Timer 8 High Hold Register
The Counter/Timer 8 High Hold Register contains the value to be counted while the T8 output is 1. Note: This register is not reset after a Stop Mode Recovery.
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Table 33. Counter/Timer 8 High Hold Register (TC8H)
Bit Field Reset R/W Address Bit Position [7:0] 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
T8_Level_HI 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bank D: 05h; Linear: D05h
Value
Description
0hh-FFh T8_Level_HI--Read/Write Data.
Counter/Timer 8 Low Hold Register
The Counter/Timer 8 Low Hold Register contains the value to be counted while the T8 output is 0. Note: This register is not reset after a Stop Mode Recovery.
Table 34. Counter/Timer 8 Low Hold Register (TC8L)
Bit Field Reset R/W Address Bit Position [7:0] R/W R/W R/W 0 0 0 7 6 5 4 3 2 1 0
T8_Level_LO 0 0 0 0 0
Bank D: 04h; Linear: D04h R/W R/W R/W R/W R/W
Value
Description
0hh-FFh T8_Level_LO--Read/Write Data.
Counter/Timer 8 Control Register
The Counter/Timer 8 Control Register controls the timer function of the T8 timer. This Bank D register is described in Table 35. Caution: Writing a 1 to CTR0[5] is the only way to reset the Terminal Count status condition. Reset this bit before using/enabling the counter/timers.
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Note:
Take care when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (DEMODULATION mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers. Example: When the status of bit 5 is 1, a timer reset condition occurs.
Table 35. Counter/Timer 8 Control Register (CTR0)
Bit Field Reset R/W Address Bit Position [7] 0 1 [6] 0 1 [5] Read: 0 1 Write: 0 1 7 T8_Enable 0 R/W 6 Single/ Modulo-N 0 R/W 5 4 3 2 1 0
Time_Out T8 _Clock 0 R/W 0 0
Capture_INT_M Counter_INT_M P34_Out ask ask 0 R/W 0 R/W 0 R/W
R/W R/W
Bank D: 00h; Linear: D00h
Value Description T8_Enable--Disable/enable the T8 counter. Disable counter. Enable counter. Configure T8 properly before enabling it. Single Pass/Modulo-N MODULO-N mode. Counter reloads the initial value when terminal count is reached SINGLE-PASS mode. Counter stops when the terminal count is reached Time_Out--This bit is set when the T8 terminal count is reached. No counter time-out occurs. Counter time-out occurred. No effect. Reset Flag to 0. Software must reset this flag before using counter/timers. T8 _Clock--Select the T8 input clock frequency. These bits are not reset upon Stop Mode Recovery. SCLK. SCLK / 2. SCLK / 4. SCLK / 8. Capture_INT_Mask--Disable/enable interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in DEMODULATION mode. This bit is not reset upon Stop Mode Recovery. Disable data capture interrupt. Enable data capture interrupt.
[4:3] 00 01 10 11 [2]
0 1
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Bit Position [1]
Value Description Counter_INT_Mask--Disable/enable T8 time-out interrupt. This bit is not reset upon Stop Mode Recovery. Disable time-out interrupt. Enable time-out interrupt. P34_Out--Select normal I/O or T8 output function for Port 3, pin 4. P34 as port output. T8 output on P34.
0 1 [0] 0 1
T8 and T16 Common Functions Register
The T8 and T16 Common Functions Register (CTR1) controls the functions in common with Timer 8 and Timer 16. Table 36 describes the bits for this register. Note: Be careful to differentiate TRANSMIT mode from DEMODULATION mode, as set by CTR1[7]. The functions of CTR1[6:0] and CTR2[6] are different depending on which mode is selected. Do not change from one mode to another without first disabling the counter/timers.
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Table 36. Timer 8 and Timer 16 Common Functions Register (CTR1)
Bit Field Reset R/W Address Bit Position [7] 0 R/W 7 Mode 6 P36 Out/ Demodulator Input 0 R/W 5 4 3 2 1 Initial Timer 8 Out/ Rising Edge 0 R/W 0 Initial Timer 16 Out/Falling Edge 0 R/W
T8/T16 Logic/ Edge Detect 0 R/W 0 R/W
Transmit Submode/ Glitch Filter 0 R/W 0 R/W
Bank D: 01h; Linear: D01h
Description Mode--Selects the TIMER mode for signal transmission or demodulation. 0 1 TRANSMIT mode. DEMODULATION mode.
[6]
TRANSMIT Mode P36 Out--Select normal I/O or timer output on Port 3, Pin 6. 0 1 P36 acts as normal I/O port output. P36 acts as combined Timer 8/Timer 16 output.
DEMODULATION Mode Demodulator Input--Select Port 2, Pin 0 or Port 3, Pin 1 as the counter/timer input. 0 1 [5:4] P31 acts as the demodulator input. If IMR[2] = 1, a P31 event can also generate an IRQ1 interrupt. To prevent this, clear IMR[2] or select P20 as input instead. P20 acts as the demodulator input.
TRANSMIT Mode T8/T16 Logic--Defines how the Timer 8/Timer 16 outputs are combined logically. These bits are not reset upon Stop Mode Recovery. 00 01 10 11 Output is T8 AND T16. Output is T8 OR T16. Output is T8 NOR T16. Output is T8 NAND T16.
DEMODULATION Mode Edge Detect--Define the behavior of the edge detector. 00 01 10 11 Falling edge detection. Rising edge detection. Falling and rising edge detection. Reserved.
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Bit Position [3:2]
Description TRANSMIT Mode Submode Selection--Select NORMAL or PING-PONG mode operation, or force T16 output. When these bits are written to 00b (NORMAL mode) or 01b (PING-PONG mode), T16_OUT assumes the opposite 0state of bit CTR1[0] until the timer begins counting. 00 01 10 11 Normal operation. Writing 00 terminates PING-PONG mode, if it is active. PING-PONG mode. Force T16_OUT = 0. Force T16_OUT = 1.
DEMODULATION Mode Glitch Filter--Define the maximum glitch width to be rejected by the counter/timer. 00 01 10 11 [1] No filter. 4 SCLK cycle filter. 8 SCLK cycle filter. Reserved.
TRANSMIT Mode Initial Timer 8 Out--Select the initial T8_OUT state when Timer 8 is enabled. While the timer is disabled, the opposite state is asserted on the pin to ensure that a transition occurs when the timer is enabled. Changing this bit while the counter is enabled can cause unpredictable output on T8_OUT. 0 1 T8_OUT transitions from High to Low when Timer 8 is enabled. T8_OUT transitions from Low to High when Timer 8 is enabled.
DEMODULATION Mode Rising Edge--Indicates whether a rising edge was detected on the input signal. Write 1 to this flag to reset it. Read: 0 1 Write: 0 1 No rising edge detection. Rising edge detection. No effect. Reset Flag to 0.
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Bit Position [0]
Description TRANSMIT Mode Initial Timer 16 Out--In NORMAL or PING-PONG mode, this bit selects the initial T16_OUT state when Timer 16 is enabled. While the timer is disabled, the opposite state is asserted on the pin to ensure that a transition occurs when the timer is enabled. Changing this bit while the counter is enabled can cause unpredictable output on T16_OUT. 0 1 If CTR1[3]=0, T16_OUT transitions from High to Low when Timer 16 is enabled. If CTR1[3]=0, T16_OUT transitions from Low to High when Timer 16 is enabled.
DEMODULATION Mode Falling Edge--Indicates whether a falling edge was detected on the input signal. Write 1 to this flag to reset it. Read: 0 1 Write: 0 1 No falling edge detection. Falling edge detection. No effect. Reset Flag to 0.
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Timer 16 Control Register
Table 37 describes the bits for the Timer 16 Control Register (CTR2). Table 37. Counter/Timer 16 Control Register (CTR2)
Bit Field Reset R/W Address Bit Position Description [7] T16_Enable--Disable/enable the T16 counter. 0 1 [6] Disable T16 counter. Enable T16 counter. 7 T16_Enable 0 R/W 6 5 4 3 2 1 0 P35_Out 0 R/W
Single/ Time_Out Modulo-N 0 R/W 0 R/W
T16 _Clock 0 R/W 0 R/W
Capture_INT Counter_INT _Mask _Mask 0 R/W 0 R/W
Bank D: 02h; Linear: D02h
TRANSMIT Mode (CTR1[7]=0) Single/Modulo-N--Selects Timer 16 terminal count action. 0 1 MODULO-N mode. T16 reloads the initial value when terminal count is reached SINGLE-PASS mode. T16 stops when the terminal count is reached
DEMODULATION Mode (CTR1[7]=1) Enable single-edge capture. See T16 DEMODULATION Mode on page 63. 0 1 [5] Timer 16 captures and reloads on all edges. Timer 16 captures and reloads on first edge only.
Time_Out--This bit is set when the T16 terminal count is reached. Read: 0 1 Write: 0 1 Time_Out--This bit is set when the T16 terminal count is reached. No counter time-out occurs. Counter time-out occurred. No effect. Reset flag to 0. Software must reset this Flag before using counter/timers.
[4:3]
T16 _Clock--Select T16 input clock frequency. These bits are not reset upon Stop Mode Recovery. 00 01 10 11 SCLK. SCLK / 2. SCLK / 4. SCLK / 8.
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Counter/Timer Registers
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Bit Position Description [2] Capture_INT_Mask--Disable/enable interrupt when data is captured into either LO16 or HI16 upon a positive or negative edge detection in DEMODULATION mode. This bit is not reset upon Stop Mode Recovery. 0 1 [1] Disable data capture interrupt. Enable data capture interrupt.
Counter_INT_Mask--Disable/enable T16 time-out interrupt. 0 1 Disable T16 time-out interrupt. Enable T16 time-out interrupt.
[0]
P35_Out--Select normal I/O or T8 output function for Port 3, pin 5. 0 1 P35 as port output. P35 is T16 output.
Timer 8/Timer 16 Control Register
The Timer 8/Timer 16 Counter/Timer Register allows the T8 and T16 counters to be synchronized. It also can freeze the T16 output value and change T8 DEMODULATION mode to capture one cycle of a carrier. Table 38 briefly describes the bits for this Bank D register. A description of each bit follows the table. Table 38. Timer 8/Timer 16 Control Register (CTR3)
Bit Field Reset R/W Address Bit Position Value [7] [6] 0 1 0 1 Description Disable T16 counter. Enable T16 counter. Configure T16 properly before enabling it. Disable T8 counter. Enable T8 counter. 7 T16_Enable 0 R/W 6 T8_Enable 0 R/W 5 Sync_Mode 0 R/W 4 T16_Out Disable 0 R/W 3 T8 Demodulate 0 R/W X -- 2 1 Reserved X -- X -- 0
Bank D: 03h; Linear: D03h
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Counter/Timer Registers
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Bit Position Value [5]
Description
SYNC Mode--When enabled, the first pulse of Timer 8 (the carrier) is always synchronized with Timer 16 (the demodulated signal). It can always provide a full carrier pulse. This bit is not reset upon Stop Mode Recovery. 0 1 Disable SYNC mode. Enable SYNC mode.
[4]
T16_Out Disable--Set this bit to disable toggling of the Timer 16 output. Time-out interrupts are still generated. This bit is not reset upon Stop Mode Recovery. 0 1 T16 toggles normally. T16 toggle is disabled. T8 captures events normally. T8 becomes active on the third edge, captures events on the fourth and fifth edges, and generates an interrupt on the fifth edge. After a T8 time-out the event count resets to 0 and the fourth and fifth edges are captured again.
[3]
T8 Demodulate--(Capture one cycle.) This bit is not reset upon Stop Mode Recovery. 0 1
[2:0]
Reserved--Always reads 111b. Writes have no effect.
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Counter/Timer Registers
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Interrupts
The Crimzon ZLR64400 MCU features six different interrupts (see Table 40 on page 81). The interrupts are maskable and prioritized (see Figure 31 on page 80). The six sources are divided as follows: three sources are claimed by Port 3 lines P33:P31, two by the counter/timers and one for low voltage detection. P32 and the UART receiver share the same interrupt. Only one interrupt can be selected as a source. When the UART receiver is enabled P32 is no longer used as an interrupt source. The UART transmit interrupt and UART baud rate interrupt use the same interrupt as the P33 interrupt. You can select which source triggers the interrupt. When bit 7 of UTCL is 1, the UART transmit interrupt is the source. When bit 7 of UCTL is 0 and bit 5 of UCTL is 1, the BRG interrupt is selected. The Interrupt Mask Register (globally or individually) enables or disables the six interrupt requests. The source for IRQ1 is determined by bit 1 of the Port 3 Mode Register (P3M) and bit 4 of the SMR4 register. If P3M[1]=0 (DIGITAL mode) and SMR4[4]=0, pin P33 is the IRQ1 source. If P3M[1]=1 (ANALOG mode) or SMR4[4]=1 (SMR interrupt enabled), the output of the Stop Mode Recovery source logic is used as the source for the interrupt. See Stop Mode Recovery Interrupt on page 92. Table 39. Interrupt Control Registers
Address (Hex) 12-Bit Bank 8-Bit 0F9 0FA 0FB All All All F9 FA FB Register Description Interrupt Priority Register Mnemonic Reset IPR XXh 00h 0XXX_XXXXb Page No 83 85 82
Interrupt Request IRQ Register Interrupt Mask Register IMR
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Interrupts
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P32
UART RX
P33
Stop-Mode Recovery Source
UCTL bits 5 & 6 = 11
0
1
0
1
P3M[1] OR SMR4[4] UART BRG Interrupt
0 1
UCTL bits 7, 6, and 0 = 001 UART TX
P31
0
1
UCTL bits 5 and 7 = 11
IRQ Register (bits 6 & 7)
Interrupt Edge Select
IRQ2 IRQ0 IRQ1
Timer 16
IRQ3
Timer 8
IRQ4
Low-Voltage Detection
IRQ5
Interrupt Request
Interrupt Mask Register 5 Interrupt Priority Register
Global Interrupt Enable Interrupt Request
Priority Logic
Vector Select
Figure 31. Interrupt Block Diagram
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Interrupts
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Table 40. Interrupt Types, Sources, and Vectors
Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Source P32, UART Rx P33, UART Tx, BRG, SMR Event P31 Timer 16 Timer 8 Vector Location (Program Memory) Comments 0,1 2,3 4,5 6,7 8,9 External (P32), Rising, Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising, Falling Edge Triggered Internal Internal Internal
Low Voltage Detection 10,11
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle activates when an interrupt request is granted. As a result, all subsequent interrupts are disabled, and the Program Counter and Status Flags are saved. The cycle then branches to the program memory vector location reserved for that interrupt. All Crimzon ZLR64400 MCU interrupts are vectored through locations in the Program Memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked, and the Interrupt Request Register is polled to determine which of the interrupt requests require service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge triggered. These interrupts are programmable. The software can poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and bit 6. The configuration is indicated in Table 41.
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Interrupts
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Table 41. Interrupt Request Register
IRQ Bit 7 0 0 1 1 6 0 1 0 1 Interrupt Edge IRQ2 (P31) F F R R/F IRQ0 (P32) F R F R/F
Note: F = Falling Edge; R = Rising Edge
Interrupt Priority Register
The Interrupt Priority Register (Table 42) defines which interrupts hold the highest priority. Interrupts are divided into three groups of two--Group A, Group B, and Group C. IPR bits 4, 3, and 0 determine which interrupt group has priority. For example, if interrupts IRQ5, IRQ1, and IRQ0 occur simultaneously when IPR[4:3, 0]=001b, the interrupts are serviced in the following order: IRQ1, IRQ0, IRQ5. IPR bits 5, 2, and 1 determine which interrupt within each group has higher priority. Table 42. Interrupt Priority Register (IPR)
Bit Field Reset R/W Address Bit Position [7:6] [5] 0 1 X -- X 7 6 5 Group A Priority X W 4 3 2 Group B Priority X W 1 Group C Priority X W 0 Group Priority [0] X W
Reserved
Group Priority [2:1] X W X
Bank Independent: F9h; Linear: 0F9h
Value Description -- Reserved Reads are undefined; writes must be 00b. Group A Priority (IRQ3, IRQ5) IRQ5 > IRQ3 IRQ3 > IRQ5
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Interrupt Priority Register
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Bit Position {[4:3], [0]}
Value Description 000 001 010 011 100 101 110 111 Group Priority Reserved C>A>B A>B>C A>C>B B>C>A C>B>A B>A>C Reserved Group B Priority (IRQ0, IRQ2) IRQ2 > IRQ0 IRQ0 > IRQ2 Group C Priority (IRQ1, IRQ4) IRQ1 > IRQ4 IRQ4 > IRQ1
[2] 0 1 [1] 0 1
Interrupt Request Register
Bits 7 and 6 of the Interrupt Request Register are used to configure the edge detection of the interrupts for Port 3, bit 1 and Port 3, bit 2. The remaining bits, 5 through 0, indicate the status of the interrupt. When an interrupt is serviced, the hardware automatically clears the bit to 0. Writing a 1 to any of these bits generates an interrupt if the appropriate bits in the Interrupt Mask Register are enabled. Writing a 0 to these bits clears the interrupts. See Table 43. Table 43. Interrupt Request Register (IRQ)
Bit Field Reset R/W Address 7 6 5 IRQ5 0 R/W 4 IRQ4 0 R/W 3 IRQ3 0 R/W 2 IRQ2 0 R/W 1 IRQ1 0 R/W 0 IRQ0 0 R/W
Interrupt Edge 0 R/W 0 R/W
Bank Independent: FAh; Linear: 0FAh
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Interrupt Request Register
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Bit Position Value Description [7:6] 00 01 10 11 [5] Read: 0 1 Write: 0 1 Read: 0 1 Write: 0 1 Read: 0 1 Write: 0 1 Read: 0 1 Write: 0 1 Read: 0 1 Write: 0 1 Read: 0 1 Write: 0 1 Interrupt Edge P31 P32 P31 P32 P31 P32 P31 P32 IRQ5 (Low Voltage Detection) Interrupt did not occur. Interrupt occurred. Clear interrupt. Set interrupt. IRQ4 (T8 Counter) Interrupt did not occur. Interrupt occurred. Clear interrupt. Set interrupt. IRQ3 (T16 Counter) Interrupt did not occur. Interrupt occurred. Clear interrupt. Set interrupt. IRQ2 (Port 3 Bit 1 Input) Interrupt did not occur. Interrupt occurred. Clear interrupt. Set interrupt. IRQ1 (Port 3 Bit 3 Input/SMR Event/UART TX/UART BRG) Interrupt did not occur. Interrupt occurred. Clear interrupt. Set interrupt. IRQ0 (Port 3 Bit 2 Input/UART RX) Interrupt did not occur. Interrupt occurred. Clear interrupt. Set interrupt.
[4]
[3]
[2]
[1]
[0]
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Interrupt Request Register
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Note:
The IRQ register is protected from change until an EI instruction is executed once.
Interrupt Mask Register
Bits [5:0] are used to enable the interrupt. Bit 7 is the status of the master interrupt. When reset, all interrupts are disabled. When writing a 1 to bit 7, you must also execute the EI instruction to enable interrupts. See Table 44. Table 44. Interrupt Mask Register (IMR)
Bit Field Reset R/W Address Bit Position [7] 7 6 5 IRQ5 Enable X R/W 4 IRQ4 Enable X R/W 3 IRQ3 Enable X R/W 2 IRQ2 Enable X R/W 1 IRQ1 Enable X R/W 0 IRQ0 Enable X R/W
Master Interrupt Reserved Enable 0 R/W X --
Bank Independent: FBh; Linear: 0FBh
Value Description Master Interrupt Enable Use only the DI and EI instructions to alter this bit. Always disable interrupts (DI instruction) before writing this register. All interrupts are disabled. Interrupts are enabled/disabled individually in bits [5:0]. Reserved Reads are undefined; writes must be 0. Disables IRQ5. Enables IRQ5. Disables IRQ4. Enables IRQ4. Disables IRQ3. Enables IRQ3. Disables IRQ2. Enables IRQ2. Disables IRQ1. Enables IRQ1. Disables IRQ0. Enables IRQ0.
0 1 [6] [5] [4] [3] [2] [1] [0] 0 0 1 0 1 0 1 0 1 0 1 0 1
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Interrupt Mask Register
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Clock
The device's on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series resistance (RS) less than or equal to 100 . The on-chip oscillator can be driven with a suitable external clock source. The crystal must be connected across XTAL1 and XTAL2 using the recommended capacitors from each pin to ground. The typical capacitor value is 10 pF for 8 MHz. Also check with the crystal supplier for the optimum capacitance.
XTAL1 C1
XTAL1
XTAL1
XTAL2 C2
XTAL2
XTAL2
Ceramic Resonator or Crystal C1, C2 = 10 pF * f = 8 MHz
External Clock
Ceramic Resonator f = 8 MHz
*Note: preliminary value, including pin parasitics.
Figure 32. Oscillator Configuration Maxim's IR MCU supports crystal, resonator, and oscillator. Most resonators have a frequency tolerance of less than 0.5%, which is enough for remote control application. Resonator has a very fast startup time, which is around few hundred microseconds. Most crystals have a frequency tolerance of less than 50 ppm (0.005%). However, crystal needs longer startup time than the resonator. The large loading capacitance slows down the oscillation startup time. Maxim suggests not to use more than 10 pF loading capacitor for the crystal. If the stray capacitance of the PCB or the crystal is high, the loading capacitance C1 and C2 must be reduced further to ensure stable oscillation before the TPOR (Power-on reset time is typically 5-6 ms. See Table 61 on page 123. For Stop Mode Recovery operation, bit 5 of SMR register allows you to select the Stop Mode Recovery delay, which is the TPOR. If Stop Mode Recovery delay is not selected, the MCU executes instruction immediately after it wakes up from the STOP mode. If resona-
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Clock
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tor or crystal is used as a clock source then Stop Mode Recovery delay needs to be selected (bit 5 of SMR = 1). For both resonator and crystal oscillator, the oscillation ground must go directly to the ground pin of the microcontroller. The oscillation ground must use the shortest distance from the microcontroller ground pin and it must be isolated from other connections.
Crystal 1 Oscillator Pin (XTAL1)
The Crystal 1 Oscillator time-based input pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. Additionally, an optional external singlephase clock can be connected to the on-chip oscillator input.
Crystal 2 Oscillator Pin (XTAL2)
The Crystal 2 Oscillator time-based output pin connects a parallel-resonant, crystal, or ceramic resonant to the on-chip oscillator output.
Internal Clock Signals (SCLK and TCLK)
The CPU and internal peripherals are driven by the internal SCLK signal during normal execution. During HALT mode, the interrupt logic is driven by the internal TCLK signal. These signals are produced by dividing the on-chip oscillator signal by a factor of two, and optionally by applying an additional divide-by-16 prescaler enabled in register bit SMR[0] (see Table 47 on page 95). This is displayed in Figure 33. Selecting the divide-by-16 prescaler reduces device power draw during normal operation and HALT mode. The prescaler is disabled by a Power-on reset or Stop Mode Recovery.
OSC
/2 SMR[0] 0 /16 1 SCLK TCLK
Figure 33. SCLK/TCLK Circuit
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Crystal 1 Oscillator Pin (XTAL1)
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Resets and Power Management
The ZLR64400 provides the following reduced-power modes, power monitoring, and reset features:
* * * * * * *
Note:
Power-On Reset--Starts the oscillator and internal clock and initializes the system to its Power-On Reset defaults. Voltage Brownout Standby--Stops the oscillator and internal clock if a low-voltage condition occurs. Initiates a Power-On Reset when power is restored. Voltage Detection--Optionally sets a Flag if a Low- or high-voltage condition occurs. The low-voltage detection Flag can generate an interrupt request, if enabled. HALT Mode--Stops the internal clock to the CPU until an enabled interrupt request is received. STOP Mode--Stops the clock and oscillator, reducing the MCU supply current to a very low level until a Power-On Reset or Stop Mode Recovery occurs. Stop Mode Recovery--Restarts the oscillator and internal clock and initializes most of the system to its Power-on reset defaults. Some register values are not reset by a Stop Mode Recovery. Watchdog Timer--Optionally generates a Power-On Reset if the program fails to execute the WDT instruction within a specified time interval.
For supply current values under various conditions, see DC Characteristics on page 120. Figure 34 on page 89 displays the Power-On Reset sources. Table 45 lists control registers for reset and power management features. Some features are affected by registers described in other chapters.
Table 45. Reset and Power Management Registers
Address (Hex) 12-Bit D0C F0A F0B F0C F0D Bank D F F F F 8-Bit Register Description 0C 0A 0B 0C 0D Low-Voltage Detection Register Stop Mode Recovery Register 4 Stop Mode Recovery Register Stop Mode Recovery Register 1 Stop Mode Recovery Register 2 Mnemonic Reset LVD SMR4 SMR SMR1 SMR2 1 1 1 1 _ 10 0 0 b XXX0 _ 00 0 0 b 0 0 1 0 _ 00 0 0 b 00h X0 X0 _ 00 XXb Page No 91 104 95 98 100
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Resets and Power Management
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Table 45. Reset and Power Management Registers (Continued)
Address (Hex) 12-Bit F0E F0F Bank F F 8-Bit Register Description 0E 0F Stop Mode Recovery Register 3 Watchdog Timer Mode Register Mnemonic Reset SMR3 WDTMR X0h XXXX_ 11 0 1 b Page No 103 105
Watchdog Timer
5-Clock Filter
CLR2* RESET
18-Clock Reset Generator
RESET
XTAL WDT TAP Select
Internal RESET Active High
Internal RC Oscillator Low Operating Voltage Detection
POR/WDT CLK CLR1
1
2
3
4
WDT/POR Counter Chain
V DD VBO
+ --
WDT 12 ns Glitch Filter From Stop-Mode Recovery Source SMR[5]
V CC
1 0
*CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers, respectively, upon a Low-to-High input translation.
Figure 34. Resets and Watchdog Timer
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Resets and Power Management
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Power-On Reset Timer
When power is initially applied to the device, a timer circuit clocked by a dedicated on-board RC-oscillator provides the Power-On Reset (POR) timer function. The POR timer circuit is a one-shot timer that keeps the internal reset signal asserted long enough for VDD and the oscillator circuit to stabilize before instruction execution begins. The reset timer is triggered by one of the following three conditions: 1. Initial power-on or recovery from a Voltage Brownout/standby condition 2. Stop Mode Recovery (if register bit SMR[5] = 1) 3. Watchdog Timer time-out SMR[5] can be cleared to 0 to bypass the POR timer upon a Stop Mode Recovery. This should only be done when using an external clock that does not require a start-up delay.
Reset/Stop Mode Recovery Status
Read-only bit SMR[7]=0 if the previous reset was initiated by a Power-on reset (including brown-out or WDT resets). SMR[7]=1 if the previous reset was initiated by a Stop Mode Recovery. A power-on, brown-out, or WDT reset restores all registers to their Power-on reset defaults. A Stop Mode Recovery restores most registers to their Power-on reset defaults. Register bits not reset by a Stop Mode Recovery are highlighted in grey in the register tables. Register bit SMR[7] is set to 1 instead of reset by a Stop Mode Recovery.
Voltage Brownout/Standby
An on-chip Voltage Comparator checks that the VDD is at the required level for correct operation of the device. Reset is globally driven when VDD falls below VBO. A small drop in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. If the VDD is allowed to stay above VRAM, the RAM content is preserved. When the power level is returned to above VBO, the device performs a Power-on reset and functions normally.
Voltage Detection
The Voltage Detection register (LVD, register 0Ch at the expanded register bank 0Dh) offers an option of monitoring the VCC voltage. The Voltage Detection is enabled when bit 0 of LVD register is set. After Voltage Detection is enabled, the VCC level is monitored in real time. The HVD Flag (bit 2 of the LVD register) is set only if VCC is higher than VHVD. The LVD Flag (bit 1 of the LVD register) is set only if VCC is lower than the VLVD.
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Power-On Reset Timer
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When Voltage Detection is enabled, the LVD flag also triggers IRQ5. The IRQ bit 5 latches the low voltage condition until it is cleared by instructions or reset. The IRQ5 interrupt is served if it is enabled in the IMR register. Otherwise, bit 5 of IRQ register is latched as a Flag only. Note: Do not modify register P01M while checking a low-voltage condition. Switching noise coming from Port 0 can trigger the LVD Flag. Voltage detection does not work in STOP mode. This register is described in Table 46 on page 91. Table 46. Low-Voltage Detection Register (LVD)
Bit Field Reset R/W Address Bit Position [7:3] [2] [1] [0] R/W -- R R R/W Value -- 0 1 0 1 0 1 1 R 1 R 7 6 5 Reserved 1 R 1 R 1 R 4 3 2 1 0
High Battery Low Battery Voltage Detect Detect Detect Enable 0 R 0 R 0 R/W
Bank D: 0Ch; Linear: D0Ch Description Reserved--Reads 11111b. Writes have no effect. HVD clear. High voltage detected. VCC>VHVD LVD clear. Low voltage detected. VCCHALT Mode
This instruction turns OFF the internal CPU clock, but not the XTAL oscillation. The counter/timers, UART, and interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after HALT mode. To enter HALT mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. Execute a NOP (Opcode = FFh) immediately before the appropriate sleep instruction, as follows:
FF 7F NOP HALT ; clear the pipeline ; enter HALT mode
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HALT Mode
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Power consumption during HALT mode can be reduced by first setting SMR[0]=1 to enable the divide-by-16 clock prescaler.
STOP Mode
This instruction turns off the internal clock and external crystal oscillation, reducing the MCU supply current to a very low level. For STOP mode current specifications, see DC Characteristics on page 120. To enter STOP mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. Execute a NOP (Opcode = FFh) immediately before the appropriate sleep instruction, as follows:
FF 6F NOP STOP ; clear the pipeline ; enter STOP mode
STOP mode is terminated only by a reset, such as WDT time-out, POR, or one of the Stop Mode Recovery events described in the following sections. This condition causes the processor to restart the application program at address 000Ch. Unlike a normal POR or WDT reset, a Stop Mode Recovery reset does not reset the contents of some registers and bits. Register bits not reset by a Stop Mode Recovery are highlighted in grey in the register tables. Register bit SMR[7] is set to 1 by a Stop Mode Recovery.
Fast Stop Mode Recovery
SMR[5] can be cleared to 0 before entering STOP mode to bypass the default TPOR reset timer upon Stop Mode Recovery. See Power-On Reset Timer on page 90. If SMR[5]=0, the Stop Mode Recovery source must be kept active for at least 10 input clock periods (TpC). Note: SMR[5] must be set to 1 if using a crystal or resonator clock source. The TPOR delay allows the clock source to stabilize before executing instructions.
Stop Mode Recovery Interrupt
Software can set register bit SMR4[4] = 1 to enable routing of Stop Mode Recovery events to IRQ1 and to Port 3, pin 3. In this configuration, if an IRQ1 interrupt occurs, register bit P3[3] = 0 indicates that a Stop Mode Recovery event is occurring.
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STOP Mode
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Stop Mode Recovery Event Sources
Any Port 2 or 3 input pin can be configured to generate a Stop Mode Recovery event, either individually or in a variety of logical combinations. The PartName provides the following registers for Stop Mode Recovery source configuration and status:
* * * * *
SMR Register--Selects one Port 3, pin 1-3 pin state or one of three Port 2 pin logical combinations to generate an event when a defined 0 or 1 level occurs. SMR1 Register--Configure one or more Port 2 input pins (0-7)to latch the latest read or write value and generate an event when the pin state changes. SMR2 Register--Selects one of seven Port 2 and 3 pin logical combinations to generate an event when a defined 0 or 1 level occurs. SMR3 Register--Configure one or more Port 3 input pins (0-3) to latch the latest read or write value and generate an event when the pin state changes. SMR4 Register--Enables routing of SMR events to IRQ1. Indicates whether port data has been latched for SMR1 or SMR3 event monitoring, and whether the latch was on a port read or write.
A Stop Mode Recovery event occurs if any of the sources defined in the SMR, SMR1, SMR2, and SMR3 registers is active.
SMR Register Events
The SMR register function is similar to the standard Stop Mode Recovery feature used in previous Z8(R) CPU-compatible parts. Register bits SMR[4:2] are set to select one of six event modes, as displayed in Figure 35 on page 94. The output of the corresponding logic is compared to the state of SMR[6]; when they are the same, a Stop Mode Recovery event is generated. If SMR[4:2]=000, no event source is selected by SMR. The state SMR[4:2]=001 is reserved and selects no event in this device. The logic configured by the SMR register ignores any port pins that are configured as an output, or that are selected as source pins in registers SMR1 or SMR3. The SMR register is summarized in Table 47 on page 95.
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STOP Mode
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SMR[4:2] = 000
VCC SMR[4:2] = 010 P31
SMR[4:2] = 011 P32
The SMR register logic ignores any pin configured as an output in the P2M or P3M registers or as a source in the SMR1 or SMR3 registers.
SMR[4:2] = 100 P33
SMR[4:2] = 101 P27 SM[4:2] = 110 P20 P23 SM[4:2] = 111 P20 P27 SMR[6] SMR
P3M[1] OR SMR4[4]
0 1
To IRQ1 And P0[3]
SMR1 SMR2 SMR3 To RESET and WDT Circuitry (Active Low)
Figure 35. SMR Register-Controlled Event Sources
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STOP Mode
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[
Table 47. Stop Mode Recovery Register (SMR)
Bit Field Reset R/W Address Bit Position Value Description [7] 0 1 [6] 0 1 [5] 0 1 [4:2] Stop Flag--Indicates whether last startup was Power-On Reset or Stop Mode Recovery. A write to this bit has no effect. Power-On Reset. Stop Mode Recovery. Stop Mode Recovery Level--Selects whether an SMR[4:2]-selected SMR is initiated by a Low or High level at the XOR-gate input (see Figure 35 on page 94). Low. High. Stop Delay--Controls the reset delay after recovery. Must be 1 if using a crystal or resonator clock source. OFF. ON. Stop Mode Recovery Source--Specifies a Stop Mode Recovery wake-up source at the XOR gate input (see Figure 35 on page 94). This value is not changed by a Stop Mode Recovery. The following equations ignore any Port pin configured as output or selected in SMR1 or SMR3. No SMR register source selected. Reserved. P31. P32. P33. P27. Port 2 NOR 0-3. Port 2 NOR 0-7. Reserved--Reads are undefined; must write 0. SCLK/TCLK Divide-by-16 Select--Controls a divide-by-16 prescaler of the internal SCLK/TCLK signal (see Internal Clock Signals (SCLK and TCLK) on page 87). A Power-On Reset or Stop Mode Recovery clears this bit to 0. OFF. ON. 7 Stop Flag 0 R 6 Stop Mode Recovery Level 0 W 5 Stop Delay 1 W 4 3 2 1 Reserved 0 W 0 SCLK/TCLK Divide-by-16 0 W
Stop Mode Recovery Source 0 W 0 W 0 W
Bank F: 0Bh; Linear: F0Bh
000 001 010 011 100 101 110 111 [1] [0] --
0 1
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STOP Mode
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SMR1 Register Events
The SMR1 register can be used to configure one or more Port 2 pins to be to be compared to a written or sampled reference value and generate a Stop Mode Recovery event when the pin state differs from the reference value. To configure a Port 2 pin as an SMR1 event source, make sure it is configured as an input in the P2M register, then set the corresponding SMR1 register bit. By default, a Stop Mode Recovery event occurs when the pin's state is zero. After a Port 2 pin is configured as an SMR1 source, any subsequent read from or write to the P2 register latches the read or written value for reference. A Stop Mode Recovery event occurs when the pin's state differs from the last reference value latched. The SMR1 source logic is displayed in Figure 36 on page 97. The program can read register bits SMR4[1:0] to determine whether the Port 2 pins trigger a Stop Mode Recovery on a change from the last read value (SMR4[1:0]=01), or on a change from the last written value (SMR4[1:0]=10). Software can clear SMR4[1:0] to 00 to restore the default behavior (configured pins trigger when their state is 0). The SMR1 register is summarized in Table 48 on page 98. After the following example code is executed, a 1 on P2 0 will wake the part from STOP mode.
LD P2M, #%FF LD SMR1, #%01 LD P2, #%00 NOP STOP ;Set Port 2 to inputs. ;Select P20 for SMR1. ;Write 00h to Port 2, so the P20 reference ;value is 0, and a 1 on P20 wakes the part.
After the following example code is executed when the value of P2 is 00h, a 1 on P20 will wake the part from STOP mode:
LD P2M, #%FF LD SMR1, #%01 LD R6, P2 NOP STOP ;Set ports to inputs. ;Select P20 for SMR1. ;If a 0 is read from Port 2, the P20 reference ;value is 0, so a 1 on P20 wakes the part.
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STOP Mode
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Individual Port 2 Pin SMR Logic, n = 0-7 Bit P2M[n] Bit SMR1[n]
To SMR1
Port 2, Pin n Bit P2[n] Port 2 Read/Write
D
Q
P33 IRQ1
P20 Logic P21 Logic P22 Logic P23 Logic P24 Logic P25 Logic P26 Logic P27 Logic
P3M[1] OR SMR4[4]
0 1 Register P3, bit 3
SMR SMR1 SMR2 SMR3 To RESET and WDT Circuitry (Active Low)
Figure 36. SMR1 Register-Controlled Event Sources
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STOP Mode
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Table 48. Stop Mode Recovery Register 1 (SMR1)
Bit Field Reset R/W Address Bit Position [7] [6] [5] [4] [3] [2] [1] [0] Value Description 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P27 not selected. P27 selected as an SMR source. P26 not selected. P26 selected as an SMR source. P25 not selected. P25 selected as an SMR source. P24 not selected. P24 selected as an SMR source. P23 not selected. P23 selected as an SMR source. P22 not selected. P22 selected as an SMR source. P21 not selected. P21 selected as an SMR source. P20 not selected. P20 selected as an SMR source. 7 P27 Stop Select 0 W 6 P26 Stop Select 0 W 5 P25 Stop Select 0 W 4 P24 Stop Select 0 W 3 P23 Stop Select 0 W 2 P22 Stop Select 0 W 1 P21 Stop Select 0 W 0 P20 Stop Select 0 W
Bank F: 0Ch; Linear: F0Ch
Note:
This register is not reset after a Stop Mode Recovery.
SMR2 Register Events
The SMR2 register function is similar to the standard Stop Mode Recovery feature used in previous Z8 CPU-compatible parts. Register bits SMR2[4:2] are set to select one of seven event modes, as displayed in Figure 37. The output of the corresponding logic is compared to the state of SMR2[6]; when they are the same, a Stop Mode Recovery event is generated. If SMR2[4:2]=000, no event source is selected by SMR2. The logic configured by the SMR2 register ignores any port pins that are configured as an output, or that are selected as source pins in registers SMR1 or SMR3.
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STOP Mode
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The SMR2 register is summarized in Table 49 on page 100.
SMR2[4:2] = 000
VCC SMR2[4:2] = 001 P20 P23 SMR2[4:2] = 010 P20 P27
The SMR2 register logic ignores any pin configured as an output in the P2M or P3M registers or as a source in the SMR1 or SMR3 registers.
SMR2[4:2] = 011
P31 P32 P33 SMR2[4:2] = 100 P31 P32 P33
P33 To IRQ1 And P0[3]
P31 P32 P33 P00 P07 P31 P32 P33 P00 P07 P31 P32 P33 P20 P21 P22
SMR2[4:2] = 101
P3M[1] OR SMR4[4]
0 1
SMR2[4:2] = 110
SMR SMR1 SMR2
SMR2[4:2] = 111
SMR3
To RESET and WDT Circuitry (Active Low)
SMR2[6]
Figure 37. SMR2 Register-Controlled Event Sources
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STOP Mode
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Table 49. Stop Mode Recovery Register 2 (SMR2)
Bit Field Reset R/W Address Bit Position [7] [6] Value Description -- Reserved--Read is undefined; write must be 0. Stop Mode Recovery Level 2 Selects whether an SMR2[4:2]-selected SMR is initiated by a Low or High level at the XOR-gate input (see Figure 37 on page 99). Low. High. Reserved--Read is undefined; write must be 0. Stop Mode Recovery Source Specifies a Stop Mode Recovery wake-up source at the XOR gate input (see Figure 37 on page 99). Additional sources can be selected by SMR, SMR1, and SMR3 registers. If more than one source is selected, any selected source event causes a Stop Mode Recovery. The following equations ignore any Port pin that is selected in register SMR1 or configured as an output. No SMR2 register source selected. NAND of P23:P20. NAND of P27:P20. NOR of P33:P31. NAND of P33:P31. NOR of P33:P31, P00, P07. NAND of P33:P31, P00, P07. NAND of P33:P31, P22:P20. Reserved--Read is undefined; write must be 00b. 7 Reserved X -- 6 Stop Mode Recovery Level 2 0 W 5 Reserved X -- 4 3 2 1 0
Stop Mode Recovery Source 0 W 0 W 0 W
Reserved X -- X
Bank F: 0Dh; Linear: F0Dh
0 1 [5] [4:2] --
000 001 010 011 100 101 110 111 [1:0] --
Note:
This register is not reset after a Stop Mode Recovery.
SMR3 Register Events
The SMR3 register can be used to configure one or more of Port 3, pins 0-3 to be compared to a written or sampled reference value and generate a Stop Mode Recovery event when the pin state differs from the reference value.
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STOP Mode
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To configure a Port 3 input pin as an SMR3 event source set the corresponding SMR3 register bit. By default, a Stop Mode Recovery event occurs when the pin's state is zero. After a Port 3 pin is configured as an SMR3 source, any subsequent read from or write to the P2 register latches the read or written value for reference. A Stop Mode Recovery event occurs when the pin's state differs from the last reference value latched. The SMR3 source logic is displayed in Figure 38 on page 102. The program can read register bits SMR4[3:2] to determine whether the Port 3 pins trigger a Stop Mode Recovery on a change from the last read value (SMR4[3:2]=01), or on a change from the last written value (SMR4[3:2]=10). Software can clear SMR4[3:2] to 00 to restore the default behavior (configured pins trigger when their state is 0). The SMR3 register is summarized in Table 47 on page 95. After the following example code is executed, a 1 on P30 will wake the part from STOP mode.
LD SMR3, #%01 LD P3, #%00 NOP STOP ;Select P30 from SMR3. ;Write 00h to Port 3, so the P30 reference ;value is 0, and a 1 on P30 wakes the part.
After the following example code is executed when the value of P3 is 00h, a 1 on P30 will wake the part from STOP mode.
LD SMR3, #%01 LD R6, P3 NOP STOP ;Select P30 for SMR3. ;If a 0 is read from Port 3, the P30 reference ;value is 0, so a 1 on P30 wakes the part.
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STOP Mode
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Individual Port 3 Pin SMR Logic, Bit SMR3[ n]
n = 0-3
To SMR3
Port 3, Pin n Bit P3[ n] Port 3 Read/Write
D
Q
P33 To IRQ1 And P0[3]
P30 Logic P31 Logic P32 Logic P33 Logic
P3M[1] OR SMR4[4]
0 1
SMR SMR1 SMR2 SMR3 To RESET and WDT Circuitry (Active Low)
Figure 38. SMR3 Register-Controlled Event Sources
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STOP Mode
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Table 50. Stop Mode Recovery Register 3 (SMR3)
Bit Field Reset R/W Address Bit Position [7:4] [3] [2] [1] [0] Value Description -- 0 1 0 1 0 1 0 1 Reserved--Reads undefined; writes have no effect. P33 not selected. P33 SMR source selected. P32 not selected. P32 SMR source selected. P31 not selected. P31 SMR source selected. P30 not selected. P30 SMR source selected. X -- X -- 7 6 -- X -- X -- 5 4 3 P33 SMR Select 0 W 2 P32 SMR Select 0 W 1 P31 SMR Select 0 W 0 P30 SMR Select 0 W
Bank F: 0Eh; Linear: F0Eh
Note:
This register is not reset after a Stop Mode Recovery.
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STOP Mode
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Stop Mode Recovery Register 4
The Stop Mode Recovery Register 4 (SMR4) Register enables the SMR interrupt source and indicates the reference value status for registers SMR1 and SMR3. Table 51. Stop Mode Recovery Register 4 (SMR4)
Bit Field Reset R/W Address Bit Position Value Description [7:5] [4] 0 1 [3:2] 00 01 10 11 [1:0] 00 01 10 11 -- Reserved--Reads are undefined; must write 000b. SMR IRQ Enable If P3M[1]=0, SMR events do not generate an interrupt. SMR events generate an interrupt on IRQ1. Port 3 SMR Status No Read or Write of the P3 register occurs. P3 Read occurs; used as SMR3 reference. P3 Write occurs; used as SMR3 reference. Reserved. Port 2 SMR Status No Read or Write of the P2 register occurs. P2 Read occurs; use P2 Read as SMR1 reference. P2 Write occurs; use P2 Write as SMR1 reference. Reserved. X -- 7 6 Reserved X -- X -- 5 4 SMR IRQ Enable 0 R/W 3 2 1 0
Port 3 SMR Status 0 R/W 0 R/W
Port 2 SMR Status 0 R/W 0 R/W
Bank F: 0Ah; Linear: F0Ah
Note:
This register is not reset after a Stop Mode Recovery.
Watchdog Timer
The Watchdog Timer (WDT) is a retriggerable one-shot timer that resets the Z8 LXM CPU if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags. The POR clock source is the internal RC-oscillator. Bits 0 and 1 of the WDT register control a tap circuit that determines the minimum time-out period. Bit 2 determines whether
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Watchdog Timer
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the WDT is active during HALT, and bit 3 determines WDT activity during STOP mode. Bits 4 through 7 are reserved (see Table 52). This register is accessible only during the first 60 processor cycles (120 XTAL clocks) from the execution of the first instruction after Power-on reset, Watchdog Timer Reset, or a Stop Mode Recovery (see STOP Mode on page 92). After this point, the register cannot be modified by any means (intentional or otherwise). The WDTMR register cannot be read. The register is located in Bank F of the Expanded Register Group at address location 0Fh. It is organized as shown in Table 52. Note: This register is not reset after a Stop Mode Recovery.
Table 52. Watchdog Timer Mode Register (WDTMR)
Bit Field Reset R/W Address Bit Position Value Description [7:4] [3] 0 1 [2] 0 1 [1:0] 00 01 10 11 -- Reserved--Reads are undefined; must write 0000. WDT During STOP Mode--Determines whether or not the WDT is active during STOP mode. OFF. WDT active during STOP mode. WDT During HALT Mode--Determines whether or not the WDT is active during HALT mode. See Figure 34. OFF. WDT active during HALT mode. Time-Out Select--Selects the WDT time period. 5 ms minimum. 10 ms minimum. 20 ms minimum. 80 ms minimum. X X X X 7 6 -- X X X X 5 4 3 2 1 0
WDT During STOP WDT During HALT Mode Mode 1 W Bank F: 0Fh; Linear: F0Fh 1 W
Time-Out Select 0 W 1 W
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Watchdog Timer
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Z8 LXM CPU Programming Summary
The following pages provide a summary of information useful for programming the Z8 LXM CPU included in this device. For details about the CPU and its instruction set, refer to Z8 LXM CPU Core User Manual (UM0183).
Addressing Notation
Table 53 summarizes Z8 LXM CPU addressing modes and symbolic notation. The text variable n represents a decimal number; aa represents a hexadecimal address; and LABEL represents a label defined elsewhere in the assembly source. In reference notation only, lowercase is used to distinguish 4-bit addressed working registers (r1, r2) from 8-bit addressed registers (R1, R2). The numerals 1 and 2, respectively, indicate whether the register is used for destination or source addressing.
.
Table 53. Symbolic Notation for Operands Assembly Symbol Operand Description cc IM - #n Condition Code cc represents a condition code mnemonic. See Condition Codes on page 110. Immediate Data IM represents an Immediate Data value, prefixed by # in assembly language. The immediate value follows the instruction opcode in program memory. n = 0 to 255. Working Register r1 or r2 represents the name, Rn, of a working register, where n = 0, 1, 2,..., 15. The equivalent 12-bit address is {RP[3:0], RP[7:4], n}. Working Register Pair rr1 or rr2 represents the name, Rn, of a working register pair, where n = 0, 2, 4,..., 14. The equivalent 12-bit address is {RP[3:0], RP[7:4], n}. Register R1 or R2 represents an 8-bit register address. For addresses 00h-DFh or F0h-FFh, the equivalent 12-bit address is {RP[3:0], %aa}. For addresses E0h-EFh (ESCAPED mode), the equivalent 12-bit address is {RP[3:0], RP[7:4], %aa[3:0]}. Register Pair (8-bit Address) RR1 or RR2 represents the 8-bit address of a register pair. For addresses 00h-DFh or F0h-FFh, the equivalent 12-bit address is {RP[3:0], %aa}. For addresses E0h-EFh (ESCAPED mode), the equivalent 12-bit address is {RP[3:0], RP[7:4], %aa[3:0]}.
r1 r2 rr1 rr2 R1 R2
Rn
RRn
%aa
RR1 RR2
%aa
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Z8 LXM CPU Programming Summary
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Table 53. Symbolic Notation for Operands (Continued) Assembly Symbol Operand Description Irr1 Irr2 @Rn Indirect Working Register Ir1 or Ir2 represents the name a working register, Rn, where n = 0, 1, 2,..., 15. @ indicates Indirect Working Register addressing using an 8-bit effective address contained in the specified working register. The accessed register's equivalent 12-bit address is {RP[3:0], 8-bit effective address}. Indirect Working Register Pair Irr1 or Irr2 represents the name a working register pair, RRn, where n = 0, 2, 4,..., 14. @ indicates Indirect Working Register addressing using an effective address in the specified working register pair. Depending on the instruction, the effective address is in the register file (12-bit address) or program/constant memory (16-bit address). Indirect Register IR1 or IR2 represents the 8-bit address of a register. @ indicates Indirect Register addressing using an 8-bit effective address contained in the specified register. The accessed register's equivalent 12-bit address is {RP[3:0], 8-bit effective address}. Indirect Register Pair IRR1 represents the 8-bit address of a register. @ indicates Indirect Register addressing with a 16-bit effective address (in program memory) contained in the specified register pair. Indexed (X) Addressing X represents the 8-bit base address to which the offset is added. r1 or r2 represents the name, Rn, of a working register containing the 8-bit signed offset. The 8-bit effective address is the sum of X and the contents of working register Rn. The accessed register's equivalent 12-bit address is {RP[3:0], 8-bit effective address}. Direct Address (JP, CALL) In a JP or CALL operand, DA is a 16-bit program memory address in the range of 0000H to FFFFH. DA replaces the contents of the Program Counter to cause execution to continue at a new location in program memory. In assembly source, the address is typically represented as a label. Relative Address (JR, DJNZ) RA is a signed 8-bit program memory offset in the range +127 to -128, relative to the address of the next instruction in program memory. In a JR or DJNZ operation, RA is added to the program counter to cause execution to continue at a new location in program memory. In assembly source, the jump address is typically represented as an absolute label, and the assembler calculates RA.
Irr1 Irr2
@RRn
IR1 IR2
@%aa
IRR1
@%aa
X(r1) X(r2)
%aa(Rn)
DA
LABEL
RA
LABEL
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Addressing Notation
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Table 54 contains additional symbols that are used throughout the instruction set summary. Table 54. Additional Symbols
Symbol dst src @ C SP PC FLAGS RP # b % h Definition Destination Operand Source Operand Indirect Address Prefix Carry Flag Stack Pointer Value Program Counter Flags Register Register Pointer Immediate Operand Prefix Binary Number Suffix Hexadecimal Number Prefix Hexadecimal Number Suffix Assignment of a value. For example, dst dst + src indicates the result is stored in the destination. Exchange of two values One's complement unary operator
~
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Addressing Notation
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Flags Register
The Flags Register informs the current status of the Z8 CPU. It contains six bits of status information. See Table 55. Table 55. Flags Register (FLAGS)
Bit Field Reset R/W Address Bit Position [7] 7 C X R/W 6 Z X R/W 5 S X R/W 4 O X R/W 3 D X R/W 2 H X R/W 1 F1 X R/W 0 F2 X R/W
Bank Independent: FCh; Linear 0FCh
Value Description Carry Flag (C) Set when the result of an arithmetic operation generates a carry out of or a borrow into the high-order bit (bit 7) of the result. Also used in rotate and shift instructions. Flag Clear Flag Set Zero Flag (Z) Set when the result of an arithmetic operation is 0. Flag Clear Flag Set Sign Flag (S) Stores the value of the most significant bit following an arithmetic, logical, rotate, or shift instruction. Flag Clear Flag Set Overflow Flag (O) Set when the result of an arithmetic operation is greater than 127. Flag Clear Flag Set Decimal Adjust Flag (D) Used for binary-coded decimal (BCD) arithmetic. Flag Clear Flag Set Half Carry Flag (H) Set when a carry out of or borrow into bit 3 of an arithmetic operation occurs. Flag Clear Flag Set
0 1 [6] 0 1 [5]
0 1 [4] 0 1 [3] 0 1 [2] 0 1
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Flags Register
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Bit Position [1]
Value Description User Flag 1 (F1) Available to software for use as a general-purpose bit. Bit Clear Bit Set User Flag 2 (F2) Available to software for use as a general-purpose bit. Bit Clear Bit Set
0 1 [0] 0 1
Condition Codes
The C, Z, S, and V Flags control the operation of the conditional jump (JP cc and JR cc) instructions. Sixteen frequently useful functions of the Flag settings are encoded in a 4-bit field called the condition code (cc). Table 56 summarizes the condition codes. Some binary condition codes can be created using more than one assembly code mnemonic. The result of the Flag test operation determines if the conditional jump executes. Table 56. Condition Codes
Binary 0000 0001 0010 0011 0100 0101 0110 0110 0111 0111 1000 1001 1010 1011 Hex 0 1 2 3 4 5 6 6 7 7 8 9 A B Assembly Mnemonic F LT LE ULE OV Ml Z EQ C ULT Definition Always False Less Than Less Than or Equal Unsigned Less Than or Equal Overflow Minus Zero Equal Carry Unsigned Less Than Flag Test Operation - (S XOR V) = 1 (Z OR (S XOR V)) = 1 (C OR Z) = 1 V=1 S=1 Z=1 Z=1 C=1 C=1 - (S XOR V) = 0 (Z OR (S XOR V)) = 0 (C = 0 AND Z = 0)
T (or blank) Always True GE GT UGT Greater Than or Equal Greater Than Unsigned Greater Than
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Condition Codes
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Table 56. Condition Codes (Continued)
Binary 1100 1101 1110 1110 1111 1111 Hex C D E E F F Assembly Mnemonic NOV PL NZ NE NC UGE Definition No Overflow Plus Non-Zero Not Equal No Carry Flag Test Operation V=0 S=0 Z=0 Z=0 C=0
Unsigned Greater Than or Equal C = 0
Z8 LXM CPU Instruction Summary
Table 57 summarizes the Z8 LXM CPU instructions. The table identifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU clock cycles required for the instruction fetch, and the number of CPU clock cycles required for the instruction execution. Table 57. Z8 LXM CPU Instruction Summary
Address Mode Symbolic Operation dst dst + src + C dst r r R R R IR ADD dst, src dst dst + src r r R R R IR src r Ir R IR IM IM r Ir R IR IM IM OpFlags code(s) (Hex) C Z S V D H 12 13 14 15 16 17 02 03 04 05 06 07 ****0* ****0* Cycles Fetch 6 6 10 10 10 10 6 6 10 10 10 10 Execute 5 5 5 5 5 5 5 5 5 5 5 5
Assembly Mnemonic ADC dst, src
Flag States: * = State Depends on Result; - = No Change; X = Undefined; 0 = Cleared; 1 = Set
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Table 57. Z8 LXM CPU Instruction Summary (Continued)
Address Mode Symbolic Operation dst dst AND src dst r r R R R IR CALL dst SP SP -2 @SP PC PC dst C ~C dst 00h dst ~dst R IR COM dst R IR CP dst, src dst - src - C r r R R R IR DA dst dst DA(dst) dst dst - 1 dst dst - 1 R IR DEC dst R IR DECW dst RR IR DI Disable Interrupts IRQCTL[7] 0 r Ir R IR IM IM IRR DA src r Ir R IR IM IM OpFlags code(s) (Hex) C Z S V D H 52 53 54 55 56 57 D4 D6 EF B0 B1 60 61 A2 A3 A4 A5 A6 A7 40 41 00 01 80 81 8F ------ -* * *-- -* * *-- * * *X-- * * * *-- -* *0-- *----- ------ ------ -* *0-- Cycles Fetch 6 6 10 10 10 10 20 20 6 6 6 6 6 6 6 10 10 10 10 8 8 6 6 10 10 6 Execute 5 5 5 5 5 5 0 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 1
Assembly Mnemonic AND dst, src
CCF CLR dst
Flag States: * = State Depends on Result; - = No Change; X = Undefined; 0 = Cleared; 1 = Set
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Table 57. Z8 LXM CPU Instruction Summary (Continued)
Address Mode Symbolic Operation dst dst - 1 if dst 0 PC PC + X Enable Interrupts IRQCTL[7] 1 HALT Mode dst dst + 1 R IR r INCW dst dst dst + 1 FLAGS @SP SP SP + 1 PC @SP SP SP + 2 IRQCTL[7] 1 PC dst DA IRR JP cc, dst JR dst JR cc, dst if cc is true PC dst PC PC + X if cc is true PC PC + X DA RA RA RR IR IRET dst r src OpFlags code(s) (Hex) C Z S V D H 0A-FA ------ Cycles Fetch
NZ/Z
Assembly Mnemonic DJNZ dst, RA
Execute
5
12/10 9F 7F 20 21 0E-FE A0 A1 BF ****** -* * *-- ------ ------ -* * *-- 6 7 6 6 6 10 10 16
EI HALT INC dst
1 0 5 5 5 5 5 0
JP dst
8D 30
------
12 8
T/F
0 0 0 0 0
0D-FD - - - - - - 8B 0B-FB ------ ------
12/10 12
T/F
12/10
Flag States: * = State Depends on Result; - = No Change; X = Undefined; 0 = Cleared; 1 = Set
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Table 57. Z8 LXM CPU Instruction Summary (Continued)
Address Mode Symbolic Operation dst src dst r r R r X(r) r R R R IR Ir IR LDC dst, src dst src dst src rr+1 rr rr + 1 dst src dst src rr+1 rr rr + 1 No operation r Irr LDCI dst, src Ir Irr r Irr LDXI dst, src Ir Irr src IM R r X(r) r Ir R IR IM IM r R Irr r Irr Ir Irr r Irr Ir OpFlags code(s) (Hex) C Z S V D H 0C-FC - - - - - - 08-F8 09-F9 C7 D7 E3 E4 E5 E6 E7 F3 F5 C2 D2 C3 D3 82 92 83 93 FF ------ ------ ------ ------ ------ Cycles Fetch 6 6 6 10 10 6 10 10 10 10 6 10 12 12 18 18 12 12 18 18 6 Execute 5 5 5 5 5 5 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0
Assembly Mnemonic LD dst, src
LDX dst, src
NOP
Flag States: * = State Depends on Result; - = No Change; X = Undefined; 0 = Cleared; 1 = Set
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Table 57. Z8 LXM CPU Instruction Summary (Continued)
Address Mode Symbolic Operation dst dst OR src dst r r R R R IR POP dst dst @SP SP SP + 1 SP SP - 1 @SP src C0 PC @SP SP SP + 2 R
C D7 D6 D5 D4 D3 D2 D1 D0 dst
Assembly Mnemonic OR dst, src
src r Ir R IR IM IM
OpFlags code(s) (Hex) C Z S V D H 42 43 44 45 46 47 50 51 70 71 CF AF 90 91 0----- ------ * * * *-- ------ ------ -* *0--
Cycles Fetch 6 6 10 10 10 10 10 10 10 12 6 14 6 6 Execute 5 5 5 5 5 5 5 5 1 1 5 0 5 5
R IR R IR
PUSH src
RCF RET RL dst
IR
RLC dst
C D7 D6 D5 D4 D3 D2 D1 D0 dst
R IR R
D7 D6 D5 D4 D3 D2 D1 D0 dst C
10 11 E0 E1
* * * *--
6 6
5 5 5 5
RR dst
* * * *--
6 6
IR
RRC dst
D7 D6 D5 D4 D3 D2 D1 D0 dst C
R IR
C0 C1
* * * *--
6 6
5 5
Flag States: * = State Depends on Result; - = No Change; X = Undefined; 0 = Cleared; 1 = Set
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Table 57. Z8 LXM CPU Instruction Summary (Continued)
Address Mode Symbolic Operation dst dst - src - C dst r r R R R IR SCF SRA dst
D7 D6 D5 D4 D3 D2 D1 D0 dst C
Assembly Mnemonic SBC dst, src
src r Ir R IR IM IM
OpFlags code(s) (Hex) C Z S V D H 32 33 34 35 36 37 DF 1----- * * *0-- ****1*
Cycles Fetch 6 6 10 10 10 10 6 6 6 Execute 5 5 5 5 5 5 5 5 5
C1 R IR
D0 D1
SRP src STOP SUB dst, src
RP src STOP Mode dst dst - src r r R R R IR dst[7:4] dst[3:0]
IM
31 6F
------ ------ ****1*
6 6 6 6 10 10 10 10
1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5
r Ir R IR IM IM
22 23 24 25 26 27 F0 F1
SWAP dst
R IR
-* *X--
8 8
TCM dst, src
(NOT dst) AND src
r r R R R IR
r Ir R IR IM IM
62 63 64 65 66 67
-* *0--
6 6 10 10 10 10
Flag States: * = State Depends on Result; - = No Change; X = Undefined; 0 = Cleared; 1 = Set
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117
Table 57. Z8 LXM CPU Instruction Summary (Continued)
Address Mode Symbolic Operation dst AND src dst r r R R R IR WDT XOR dst, src dst dst XOR src r r R R R IR r Ir R IR IM IM src r Ir R IR IM IM OpFlags code(s) (Hex) C Z S V D H 72 73 74 75 76 77 5F B2 B3 B4 B5 B6 B7 ------ -* *0-- -* *0-- Cycles Fetch 6 6 10 10 10 10 6 6 6 10 10 10 10 Execute 5 5 5 5 5 5 0 5 5 5 5 5 5
Assembly Mnemonic TM dst, src
Flag States: * = State Depends on Result; - = No Change; X = Undefined; 0 = Cleared; 1 = Set
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Z8 LXM CPU Instruction Summary
ZLR64400 ROM MCU Product Specification
118
Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than those listed in Table 58 may cause permanent damage to the device. These ratings are stress ratings only. Functional operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS). Table 58. Absolute Maximum Ratings
Parameter Ambient temperature under bias Storage temperature Voltage on any pin with respect to VSS* Voltage on VDD pin with respect to VSS Maximum current on input and/or inactive output pin Maximum output current from active output pin Maximum current into VDD or out of VSS
*This voltage applies to all pins except VDD, P32, and P33.
Minimum Maximum Units 0 -65 -0.3 -0.3 -5 -25 +70 +150 +4.0 +3.6 +5 +25 75 C C V V A mA mA
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Electrical Characteristics
ZLR64400 ROM MCU Product Specification
119
Standard Test Conditions
The characteristics listed in this product specification apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (see Figure 39).
From Output Under Test
I
150 pF
Figure 39. Test Load Diagram
Capacitance
Table 59 lists the capacitances. Table 59. Capacitance
Parameter Input capacitance Output capacitance I/O capacitance Maximum 12 pF 12 pF 12 pF
Note: TA = 25 C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND.
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Standard Test Conditions
ZLR64400 ROM MCU Product Specification
120
DC Characteristics
Table 60 describes the direct current characteristics of the ZLR64400 ROM MCU. Table 60.DC Characteristics
TA = 0 C to +70 C Symbol VCC VCH VCL VIH VIL VOH1 VOH2 Parameter Supply Voltage1 Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output High Voltage (P36, P37, P00, P01) Output Low Voltage Output Low Voltage (P00, P01, P36, P37) 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 VCC Minimum 2.0 0.8 VCC VSS-0.3 0.7 VCC VSS-0.3 VCC-0.4 VCC-0.8 Typ6 Maximum Units Conditions 3.6 VCC+0.3 0.4 VCC+0.3 0.2 VCC V V V V V V V IOH = -0.5 mA IOH = -7 mA See note 1 Driven by External Clock Generator Driven by External Clock Generator
VOL1 VOL2
2.0-3.6 2.0-3.6
0.4 0.8
V V
IOL = 4.0 mA IOL = 10 mA
VOFFSET Comparator Input Offset Voltage VREF IIL IIL1 RPU Comparator Reference Voltage Input Leakage Input Leakage IR Amp (P31) Pull-up Resistance
2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0 3.6 0 -1 -2.5 225 75 -1 1.2 2.2
25 Vcc -1.75 1 -12 675 275 1 3 5
mV V
A A
k k
VIN = 0 V, VCC; pullups disabled. VIN = 0 V, IR amp enabled. VIN = 0 V; Pull-ups selected by mask option VIN = 0 V, VCC at 8.0 MHz at 8.0 MHz
IOL ICC
Output Leakage Supply Current
2,3
2.0-3.6 2.0 3.6
A
mA mA
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DC Characteristics
ZLR64400 ROM MCU Product Specification
121
Table 60.DC Characteristics (Continued)
TA = 0 C to +70 C Symbol ICC1 ICC2 Parameter Standby Current2,3 (HALT mode) Standby Current4 (STOP mode) VCC 2.0 3.6 2.0 3.6 2.0 3.6 ILV VBO VLVD VHVD Standby Current5 (Low Voltage) VCC Low Voltage Protection VCC Low Voltage Detection VCC High Voltage Detection 2.0-3.6 2.0-3.6 10 Minimum Typ6 0.5 0.8 1.3 1.8 5.8 8.9 0.9 1.8 2.4 2.7 20 100 Maximum Units Conditions 1.6 2.0 8 10 20 30 6 2.0 mA mA A A A A VIN = 0 V, VCC at 8.0 MHz VIN = 0 V, VCC WDT is not running VIN = 0 V, VCC WDT is running Measured at 1.3 V
A
V V V
TONIRAMP Wake-up time from disabled mode IDET IR amp current for signal detection
s A
IR amp enabled
Notes 1. Maxim recommends adding a filter capacitor (minimum 0.1 F), physically close to VDD and VSS if operating voltage fluctuations are anticipated, such as those resulting from driving an infrared LED. 2. All outputs unloaded, inputs at rail. 3. CL1 = CL2 = 10 pF. 4. Oscillator stopped. 5. Oscillator stops when VCC falls below VBO limit. 6. Typical values shown are at 25 C.
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DC Characteristics
ZLR64400 ROM MCU Product Specification
122
AC Characteristics
Figure 40 and Table 61 on page 123 describe the Alternating Current (AC) characteristics.
1
3
Clock
2 7 7 2 3
TIN
4 6 5
IRQN
8 9
Clock Setup
1 1
Stop-Mode Recovery Source
1 0
Figure 40. AC Timing Diagram
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AC Characteristics
ZLR64400 ROM MCU Product Specification
123
Table 61.AC Characteristics
TA = 0 C to +70 C 8.0 MHz No 1 2 3 4 Symbol T PC TRC,TFC T WC TWTINL TWTINH TPTIN TRTIN,TFTIN TWIL TWIH TWSM Parameter Input Clock Period1 Clock Input Rise and Fall Times1 Input Clock Width1 Timer Input Low Width1 Timer Input High Width1 Timer Input Period1 Timer Input Rise and Fall Timers1 Interrupt Request Low Time1,2 VCC 2.0-3.6 2.0-3.6 2.0-3.6 2.0 3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0 3.6 100 70 5TPC 123 10TPC4 11 12 TOST TWDT Oscillator Start-Up Time4 Watchdog Timer Delay Time 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 13 14 TPOR firamp Power-On Reset Frequency of input signal for IR amplifier 2.0-3.6 5 10 20 80 2.5 0 10 500 5TPC ms ms ms ms ms kHz 0, 0 0, 1 1, 0 1, 1 ns 37 100 70 3TPC 8TPC 100 ns ns ns Minimum Maximum 121 DC 25 Units ns ns ns ns ns
WDTMR (Bits 1:0)
5 6 7 8
9 10
Interrupt Request Input 2.0-3.6 High Time1,2 Stop Mode Recovery Width Spec 2.0-3.6
Notes 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33:P31). 3. SMR - bit 5 = 1. 4. SMR - bit 5 = 0.
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AC Characteristics
ZLR64400 ROM MCU Product Specification
124
Packaging
Figure 41 displays the 28-pin shrink small outline package (SSOP) for the ZLR64400 device.
D 28 15 C SYMBOL A E H A1 A2 B C 1 14 DETAIL A D E e
Q1
MILLIMETER MIN 1.73 0.05 1.68 0.25 0.09 10.07 5.20 10.20 5.30 0.65 TYP 7.65 0.63 7.80 0.75 7.90 0.95 0.301 0.025 NOM 1.86 0.13 1.73 MAX 1.99 0.21 1.78 0.38 0.20 10.33 5.38 MIN 0.068 0.002 0.066 0.010 0.004 0.397 0.205
INCH NOM 0.073 0.005 0.068 MAX 0.078 0.008 0.070 0.015 0.006 0.402 0.209 0.0256 TYP 0.307 0.030 0.311 0.037 0.008 0.407 0.212
H L A2
A1
A
e
B SEATING PLANE CONTROLLING DIMENSIONS: MM LEADS ARE COPLANAR WITHIN .004 INCHES. L
0-8
DETAIL 'A'
Figure 41. 28-Pin SSOP Package Diagram
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Packaging
ZLR64400 ROM MCU Product Specification
125
Figure 42 displays the 28-pin small outline integrated circuit (SOIC) package for the ZLR64400 device.
Figure 42. 28-Pin SOIC Package Diagram
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Packaging
ZLR64400 ROM MCU Product Specification
126
Figure 43 displays the 28-pin plastic dual inline package (PDIP) for the ZLR64400 device.
Figure 43. 28-Pin PDIP Package Diagram
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Packaging
ZLR64400 ROM MCU Product Specification
127
Figure 44 displays the 20-pin shrink small outline package (SSOP) for the ZLR64400 device.
Figure 44. 20-Pin SSOP Package Diagram
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Packaging
ZLR64400 ROM MCU Product Specification
128
Figure 45 displays the 20-pin small outline integrated circuit (SOIC) package for the ZLR64400 device.
Figure 45. 20-Pin SOIC Package Diagram
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Packaging
ZLR64400 ROM MCU Product Specification
129
Figure 46 displays the 20-pin plastic dual inline package (PDIP) for the ZLR64400 device.
Figure 46. 20-Pin PDIP Package Diagram
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Packaging
ZLR64400 ROM MCU Product Specification
130
Ordering Information
Table 62 provides a product specification index code and a brief description of each part. Each of the parts listed in Table 62 is shown in a lead-free package. The use of lead-free packaging adheres to a socially responsible environmental standard. See the Part Number Description on page 131 for a description of a part number's unique identifying attributes. Table 62. ZLR64400 ROM MCU Part Numbers Description
PSI No ZLR64400H2864G ZLR64400S2864G ZLR64400P2864G ZLR64400H2064G ZLR64400S2064G ZLR64400P2064G ZLR64400X2064O ZLR64400X2864O Development Tools ZLP128ICE01ZEMG* Crimzon In-Circuit Emulator Description 28-pin SSOP 64K ROM 28-Pin SOIC 64K ROM 28-Pin PDIP 64K ROM 20-Pin SSOP 64K ROM 20-pin SOIC 64K ROM 20-pin PDIP 64K ROM 20-pin 64K ROM DIE 28-pin 64K ROM DIE PSI No ZLR64400H2832G ZLR64400S2832G ZLR64400P2832G ZLR64400H2032G ZLR64400S2032G ZLR64400P2032G ZLR64400X2032O ZLR64400X2832O Description 28-pin SSOP 32K ROM 28-Pin SOIC 32K ROM 28-Pin PDIP 32K ROM 20-Pin SSOP 32K ROM 20-pin SOIC 32K ROM 20-pin PDIP 32K ROM 20-pin 32K ROM DIE 28-pin 32K ROM DIE
Note: *ZLP128ICE01ZEMG has been replaced by an improved version, ZCRMZNICE01ZEMG.
ZCRMZNICE01ZEMG ZCRMZN00100KITG ZCRMZNICE01ZACG ZCRMZNICE02ZACG
Crimzon In-Circuit Emulator Crimzon In-Circuit Emulator Development Kit 20-Pin Accessory Kit 40/48-Pin Accessory Kit
For complete details on ZLR64400 ROM MCU, development tools and downloadable software, refer to www.maxim-ic.com/microcontrollers.
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Ordering Information
ZLR64400 ROM MCU Product Specification
131
Part Number Description
Maxim part numbers consist of a number of components, as shown in Figure 47. The example part number ZLR64400H2864G is a Crimzon 64K ROM product in a 28-pin SSOP package, with 64KB of ROM and built using lead-free solder.
ZLR64400H2864G
Environmental Flow G = Lead Free Memory Size 32 = 32 KB ROM 64 = 64 KB OTP Number of Pins in Package 20 = 20 Pins 28 = 28 Pins Package Type H = SSOP S = SOIC P = PDIP X = DIE SALES Product Number: 64400 Product Line: Crimzon ROM Maxim Product Prefix
Figure 47. Part Number Example
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Part Number Description
ZLR64400 ROM MCU Product Specification
132
Index
Numerics
12-bit address map 33 16-bit counter/timer circuits 62 20-pin package pins 5, 6 PDIP package 129 SOIC package 128 SSOP package 127 28-pin package pins 7, 8, 9 PDIP package 126 SOIC package 125 SSOP package 124 8-bit counter/timer circuits 57 counter/timer 53 interrupt 80 MCU 4 reset and watch-dog timer 89 UART 41 brown-out, voltage 90
C
capacitance 119 caution open-drain output 10 stopping timer 57 timer count 57 timer modes 72 timer registers 63 UART transmit 43, 44 characteristics AC 122, 123 DC 120 electrical 118 clock 86 internal signals 87 CMOS gate, caution 10 comparator inputs 18 outputs 18 condition codes 110 conditions, test 119 connection, power 3 constant memory 26, 27 constant, baud rate 52 counter/timer block diagram 53 capture flowchart 59 input circuit 55 output configuration 17 crystal 86 crystal oscillator pins (XTAL1, XTAL2) 86, 87 Customer Feedback Form 138
A
absolute maximum ratings 118 AC characteristics 122, 123 AC timing 122 active low notation 3 address 12-bit linear 33 notation 106 amplifier, infrared 39 AND caution 71 architecture MPU 1 UART 40 asynchronous data 42
B
baud rate generator description 47 example 49 interrupt 47 Baud Rate Generator Constant register (BCNST) 52 block diagram
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Index
ZLR64400 ROM MCU Product Specification
133
D
data format, UART 42 data handling, UART 46 DC characteristics 120 demodulation changing mode 72 flowchart 59, 60 timer 58, 63 demodulation mode flowchart 61 device architecture 1 block diagram 4 features 1 part numbers 130 diagram, package 124, 125, 126, 127, 128, 129 divisor, baud rate 52
handshaking, UART 45
I
I/O port pin functions 10 infrared learning amplifier 39 input comparator 18 counter/timer 55 timers 54 instruction set summary 111 instruction symbols 108 internal clock 87 interrupt baud rate generator 47 block diagram 80 description 79 mask register 85 priority register 82 request register 82, 83 source 81 stop-mode recovery 92 type 81 UART 45 UART receive 44, 45, 47 UART transmit 43, 45 vector 81 Interrupt Mask Register (IMR) 85 Interrupt Priority Register (IPR) 82 Interrupt Request Register (IRQ) 82, 83
E
electrical characteristics 118 error handling, UART 46 example BCNST register 49 register pointer 31
F
fast recovery, stop mode 92 features, device 1 flags register 109 floating CMOS gate, caution 10 flowchart demodulation mode 59, 60, 61 timer transmit 56 UART receive 47 format, UART data 42 functional block diagram 4 functions, I/O port pins 10
L
LDE and LDEI instructions removed 32 LDX, LDXI instruction addresses 33 leakage, caution 10 learning amplifier, infrared 39 linear address 31 load, test 119 Low-Voltage Detection Register (LVD) 91
H
h suffix 57 HALT mode 91
M
map
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Index
ZLR64400 ROM MCU Product Specification
134
program/constant memory 27 register 12-bit 33 register 8-bit 29 register file summary 36 maximum ratings 118 MCU block diagram 4 features 1 part numbers 130 memory address, linear 31 program/constant 26 program/constant map 27 register 12-bit map 33 register file map 29 register file summary 36 modulo-N mode 58, 63 MPU architecture 1
P
package diagram 124, 125, 126, 127, 128, 129 package information 124 parity, UART data 42 part number format 130, 131 pin description 5 pin function port 0 11 port 2 12 port 3 13 port 3 summary 16 ping-pong mode 64, 65 pins 20-pin package 5, 6 28-pin package 7, 8, 9 polled UART receive 44 polled UART transmit 42 port 0 configuration 12 pin function 11 Port 0 Mode Register (P01M) 19 Port 0 Register (P0) 20 port 2 configuration 13 pin function 12 Port 2 Mode Register (P2M) 21 Port 2 Register (P2) 22 port 3 configuration 14 counter/timer output 17 pin function 13 pin function 16 Port 3 Mode Register (P3M) 23 Port 3 Register (P3) 24 Port Configuration Register (PCON) 18 port pin functions 10 power connection 3 power management 88 power-on reset timer 90 program memory description 26 map 27 Program Memory Paging Register (PMPR) 34 programming summary 106
N
notation addressing 106 operand 106
O
open-drain output caution 10 operand symbols 106 operation, UART 41 OR caution 71 ordering information 130 oscillator 86 OTP memory 26 output comparator 18 timer/counter 65 timer/counter circuit 66 timer/counter configuration 17 overline, in text 3 overrun, UART 46
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Index
ZLR64400 ROM MCU Product Specification
135
pull-up, disabled 10
R
ratings, maximum 118 register BCNST 52 CTR1 73 CTR3 77 HI16 68 HI8 67 IMR 85 IPR 82 IRQ 82, 83 LO16 68 LO8 67 LVD 91 P0 20 P01M 19 P2 22 P2M 21 P3 24 P3M 23 PCON 18 PMPR 34 RP 34 SMR 95 SMR1 98 SMR2 100 SMR3 103 SMR4 104 SPL 35 UCTL 51 URDATA 49 USER 35 UST 50 UTDATA 49 WDTMR 105 register file 12-bit address 33 address summary 36 description 27 memory map 29 register pointer
detail 30 example 31 Register Pointer Register (RP) 34 Register Pointer register (RP) 34 reset block diagram 89 delay bypass 92 features 88 POR timer 90 status 90 timer terminal count 70
S
SCLK signal 87 single-pass mode 58, 63 source interrupt 81 stop-mode recovery 93, 94, 97, 99, 102 stack 28 Stack Pointer Register (SPL) 35 standard test conditions 119 standby, brown-out 90 status reset 90 UART 50 stop bit, UART 46 stop mode fast recovery 92 stop-mode description 92 recovery events 93, 96, 98, 100 recovery interrupt 92 recovery source 93, 94, 97, 99, 102 recovery status 90 Stop-Mode Recovery Register (SMR) 95 Stop-Mode Recovery Register 1 (SMR1) 98 Stop-Mode Recovery Register 2 (SMR2) 100 Stop-Mode Recovery Register 3 (SMR3) 103 Stop-Mode Recovery Register 4 (SMR4) 104 suffix, h 57 symbols address 106 instruction 108
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Index
ZLR64400 ROM MCU Product Specification
136
operand 106
T
T16_OUT signal modulo-N mode 63 single-pass mode 63 T8_OUT signal modulo-N mode 58 single-pass mode 58 TCLK signal 87 terminal count, reset 70 test conditions 119 test load 119 timer block diagram 53 changing mode 72 description 53 input circuit 54, 55 output circuit 66 output configuration 17 output description 65 reset 90 starting count caution 57 stopping caution 57 T16 demodulation 63 T16 transmit 62 T16_OUT signal 63 T8 demodulation 58 T8 transmit 55 T8_OUT signal 58 transmit flowchart 56 transmit versus demodulation mode 72 Timer 16 Capture High Register (HI16) 68 Timer 16 Capture Low Register (L016) 68 Timer 16 Control register (CTR2) 76 Timer 16 High Hold register (TC16H) 68, 69 Timer 16 Low Hold Register (TC16L) 69 Timer 8 and Timer 16 Common Functions Register (CTR1) 73 Timer 8 Capture High Register (HI8) 67 Timer 8 Capture Low Register (L08) 67 Timer 8 Control Register (CTR0) 70, 71 Timer 8 High Hold Register (TC8H) 69, 70
Timer 8 Low Hold Register (TC8L) 70 Timer 8/Timer 16 Control Register (CTR3) 77 timing, AC 122 transmit caution, UART 43, 44 transmit mode caution 72 flowchart 56 timer 55, 62
U
UART architecture 40 baud rate generator 47 block diagram 41 data and error handling 46 data format 42 description 40 interrupts 45 operation 41 overrun error 46 polled receive 44 polled transmit 42 receive interrupt 44, 45, 47 stop bit 46 transmit caution 43, 44 transmit interrupt 43, 45 UART Control Register (UCTL) 51 UART Receive/Transmit Data Register (URDATA/UTDATA) 49 UART Status Register (UST) 50 User Data Register (USER) 35
V
vector, interrupt 81 voltage brown-out 90 detection 90 detection register 91
W
watch-dog timer
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Index
ZLR64400 ROM MCU Product Specification
137
description 104 diagram 89 Watch-Dog Timer Mode Register (WDTMR) 105
X
XTAL1 pin 86 XTAL2 pin 87
Z
ZLR64400 MCU block diagram 4 features 1 part numbers 130
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Index
ZLR64400 ROM MCU Product Specification
138
Customer Support
For answers to technical questions about the product, documentation, or any other issues with Maxim's offerings, please go to https://support.maxim-ic.com/micro.
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Customer Support

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